FR2837611B1 - Circuit de conservation de donnees - Google Patents

Circuit de conservation de donnees

Info

Publication number
FR2837611B1
FR2837611B1 FR0214516A FR0214516A FR2837611B1 FR 2837611 B1 FR2837611 B1 FR 2837611B1 FR 0214516 A FR0214516 A FR 0214516A FR 0214516 A FR0214516 A FR 0214516A FR 2837611 B1 FR2837611 B1 FR 2837611B1
Authority
FR
France
Prior art keywords
data retention
retention circuit
circuit
data
retention
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR0214516A
Other languages
English (en)
Other versions
FR2837611A1 (fr
Inventor
Yukio Arima
Takahiro Yamashita
Koichiro Ishibashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Technology Academic Research Center
Original Assignee
Semiconductor Technology Academic Research Center
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Technology Academic Research Center filed Critical Semiconductor Technology Academic Research Center
Publication of FR2837611A1 publication Critical patent/FR2837611A1/fr
Application granted granted Critical
Publication of FR2837611B1 publication Critical patent/FR2837611B1/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037—Bistable circuits
    • H03K3/0375—Bistable circuits provided with means for increasing reliability; for protection; for ensuring a predetermined initial state when the supply voltage has been applied; for storing the actual state when the supply voltage fails
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/16—Modifications for eliminating interference voltages or currents
    • H03K17/161—Modifications for eliminating interference voltages or currents in field-effect transistor switches
    • H03K17/162—Modifications for eliminating interference voltages or currents in field-effect transistor switches without feedback from the output circuit to the control circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/16—Modifications for eliminating interference voltages or currents
    • H03K17/161—Modifications for eliminating interference voltages or currents in field-effect transistor switches
    • H03K17/165—Modifications for eliminating interference voltages or currents in field-effect transistor switches by feedback from the output circuit to the control circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/0033—Radiation hardening
    • H03K19/00338—In field effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/356104—Bistable circuits using complementary field-effect transistors
    • H03K3/356113—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit
    • H03K3/356147—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit using pass gates
    • H03K3/356156—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit using pass gates with synchronous operation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/3565—Bistables with hysteresis, e.g. Schmitt trigger

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Semiconductor Memories (AREA)
  • Logic Circuits (AREA)
  • Static Random-Access Memory (AREA)
  • Dram (AREA)
FR0214516A 2002-03-19 2002-11-20 Circuit de conservation de donnees Expired - Fee Related FR2837611B1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2002076789A JP3744867B2 (ja) 2002-03-19 2002-03-19 データ保持回路

Publications (2)

Publication Number Publication Date
FR2837611A1 FR2837611A1 (fr) 2003-09-26
FR2837611B1 true FR2837611B1 (fr) 2005-10-14

Family

ID=27800374

Family Applications (1)

Application Number Title Priority Date Filing Date
FR0214516A Expired - Fee Related FR2837611B1 (fr) 2002-03-19 2002-11-20 Circuit de conservation de donnees

Country Status (4)

Country Link
US (4) US6922094B2 (fr)
JP (1) JP3744867B2 (fr)
CN (1) CN100351949C (fr)
FR (1) FR2837611B1 (fr)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7873589B2 (en) * 2001-04-02 2011-01-18 Invivodata, Inc. Operation and method for prediction and management of the validity of subject reported data
US7721183B2 (en) * 2004-08-30 2010-05-18 California Institute Of Technology Method and apparatus for providing SEU-tolerant circuits
JP4551731B2 (ja) 2004-10-15 2010-09-29 株式会社東芝 半導体集積回路
CN101069351A (zh) * 2004-12-01 2007-11-07 皇家飞利浦电子股份有限公司 具有逻辑电路的电子器件和设计逻辑电路的方法
JP2006339355A (ja) * 2005-06-01 2006-12-14 Nec Electronics Corp 半導体集積回路装置及びその設計方法
US7323920B2 (en) * 2005-06-13 2008-01-29 Hewlett-Packard Development Company, L.P. Soft-error rate improvement in a latch using low-pass filtering
JP2007073709A (ja) 2005-09-06 2007-03-22 Nec Electronics Corp 半導体装置
JP2007124343A (ja) 2005-10-28 2007-05-17 Toshiba Corp データ保持回路
US7405606B2 (en) * 2006-04-03 2008-07-29 Intellectual Ventures Fund 27 Llc D flip-flop
JP4954639B2 (ja) 2006-08-25 2012-06-20 パナソニック株式会社 ラッチ回路及びこれを備えた半導体集積回路
JP2008112857A (ja) 2006-10-30 2008-05-15 Nec Electronics Corp 半導体集積回路装置
JPWO2008133215A1 (ja) * 2007-04-19 2010-07-22 国立大学法人 千葉大学 半導体集積回路
US7570080B2 (en) * 2007-09-28 2009-08-04 Intel Corporation Set dominant latch with soft error resiliency
JP2009302903A (ja) * 2008-06-13 2009-12-24 Toshiba Corp 半導体集積回路
JP2010045610A (ja) * 2008-08-13 2010-02-25 Toshiba Corp 半導体集積回路
TWI404029B (zh) * 2008-10-08 2013-08-01 Au Optronics Corp 具低漏電流控制機制之閘極驅動電路
JP2013102095A (ja) * 2011-11-09 2013-05-23 Toshiba Corp 半導体集積回路装置
JP2014195241A (ja) * 2013-02-28 2014-10-09 Semiconductor Energy Lab Co Ltd 半導体装置
WO2021071426A1 (fr) * 2019-10-08 2021-04-15 Zero-Error Systems Pte. Ltd. Circuit pour atténuer des phénomènes transitoires d'événement unique

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US525923A (en) * 1894-09-11 Ice-handling implement
US5157625A (en) * 1990-05-22 1992-10-20 United Technologies Corporation Radiation resistant sram memory cell
US5111429A (en) * 1990-11-06 1992-05-05 Idaho Research Foundation, Inc. Single event upset hardening CMOS memory circuit
US5311070A (en) * 1992-06-26 1994-05-10 Harris Corporation Seu-immune latch for gate array, standard cell, and other asic applications
JP3667787B2 (ja) * 1994-05-11 2005-07-06 株式会社ルネサステクノロジ 半導体記憶装置
US5525923A (en) 1995-02-21 1996-06-11 Loral Federal Systems Company Single event upset immune register with fast write access
US6026011A (en) 1998-09-23 2000-02-15 Intel Corporation CMOS latch design with soft error immunity
US6259643B1 (en) * 1999-05-28 2001-07-10 Systems Integration Inc. Single event upset (SEU) hardened static random access memory cell
WO2001010026A1 (fr) 1999-07-28 2001-02-08 Lockheed Martin Corporation Circuit bascule insensible aux particules ionisantes isolees ameliore
US6392474B1 (en) * 1999-09-07 2002-05-21 Bae Systems Information And Electronic Systems Integration Inc. Circuit for filtering single event effect (see) induced glitches
US6356101B1 (en) * 1999-12-28 2002-03-12 Honeywell International Inc. Glitch removal circuitry
US6327176B1 (en) * 2000-08-11 2001-12-04 Systems Integration Inc. Single event upset (SEU) hardened latch circuit

Also Published As

Publication number Publication date
FR2837611A1 (fr) 2003-09-26
US6922094B2 (en) 2005-07-26
CN100351949C (zh) 2007-11-28
JP2003273709A (ja) 2003-09-26
US20050231257A1 (en) 2005-10-20
US20050242863A1 (en) 2005-11-03
US7132871B2 (en) 2006-11-07
US7167033B2 (en) 2007-01-23
CN1445786A (zh) 2003-10-01
JP3744867B2 (ja) 2006-02-15
US20030179031A1 (en) 2003-09-25
US20050248379A1 (en) 2005-11-10
US7151395B2 (en) 2006-12-19

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Legal Events

Date Code Title Description
TP Transmission of property
PLFP Fee payment

Year of fee payment: 14

PLFP Fee payment

Year of fee payment: 15

ST Notification of lapse

Effective date: 20180731