DE602005001266D1 - Speicherbaustein mit mehrfunktions-strobe-anschlüssen - Google Patents

Speicherbaustein mit mehrfunktions-strobe-anschlüssen

Info

Publication number
DE602005001266D1
DE602005001266D1 DE602005001266T DE602005001266T DE602005001266D1 DE 602005001266 D1 DE602005001266 D1 DE 602005001266D1 DE 602005001266 T DE602005001266 T DE 602005001266T DE 602005001266 T DE602005001266 T DE 602005001266T DE 602005001266 D1 DE602005001266 D1 DE 602005001266D1
Authority
DE
Germany
Prior art keywords
transceivers
memory device
transfer
data
memory block
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602005001266T
Other languages
English (en)
Other versions
DE602005001266T2 (de
Inventor
Joo S Choi
Troy A Manning
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Micron Technology Inc
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Publication of DE602005001266D1 publication Critical patent/DE602005001266D1/de
Application granted granted Critical
Publication of DE602005001266T2 publication Critical patent/DE602005001266T2/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1063—Control signal output circuits, e.g. status or busy flags, feedback command signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1066—Output synchronization
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/109—Control signal input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1093—Input synchronization
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/2254—Calibration

Landscapes

  • Dram (AREA)
  • Detection And Correction Of Errors (AREA)
  • Information Transfer Systems (AREA)
  • Error Detection And Correction (AREA)
DE602005001266T 2004-01-27 2005-01-11 Speicherbaustein mit mehrfunktions-strobe-anschlüssen Active DE602005001266T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US765310 2004-01-27
US10/765,310 US7508722B2 (en) 2004-01-27 2004-01-27 Memory device having strobe terminals with multiple functions
PCT/US2005/000809 WO2005073974A1 (en) 2004-01-27 2005-01-11 Memory device having multiple-function strobe terminals

Publications (2)

Publication Number Publication Date
DE602005001266D1 true DE602005001266D1 (de) 2007-07-12
DE602005001266T2 DE602005001266T2 (de) 2008-01-24

Family

ID=34795451

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602005001266T Active DE602005001266T2 (de) 2004-01-27 2005-01-11 Speicherbaustein mit mehrfunktions-strobe-anschlüssen

Country Status (9)

Country Link
US (3) US7508722B2 (de)
EP (1) EP1709644B1 (de)
JP (1) JP4747342B2 (de)
KR (1) KR100779284B1 (de)
CN (2) CN101740106A (de)
AT (1) ATE363715T1 (de)
DE (1) DE602005001266T2 (de)
TW (1) TWI282097B (de)
WO (1) WO2005073974A1 (de)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7508722B2 (en) * 2004-01-27 2009-03-24 Micron Technology, Inc. Memory device having strobe terminals with multiple functions
US7116600B2 (en) * 2004-02-19 2006-10-03 Micron Technology, Inc. Memory device having terminals for transferring multiple types of data
KR100954109B1 (ko) * 2008-08-29 2010-04-23 주식회사 하이닉스반도체 데이터 입력회로 및 이를 포함하는 반도체 메모리장치
US8004887B2 (en) * 2008-11-07 2011-08-23 Micron Technology, Inc. Configurable digital and analog input/output interface in a memory device
KR101039862B1 (ko) * 2008-11-11 2011-06-13 주식회사 하이닉스반도체 클럭킹 모드를 구비하는 반도체 메모리장치 및 이의 동작방법
US9472246B2 (en) 2012-11-07 2016-10-18 Freescale Semiconductor, Inc. Method and apparatus for maintaining an accurate I/O calibration cell
TWI506443B (zh) * 2012-12-27 2015-11-01 Mediatek Inc 處理器與週邊裝置之間的媒介週邊介面及其通信方法
US9472261B1 (en) * 2015-04-17 2016-10-18 Qualcomm Incorporated Systems and methods to refresh DRAM based on temperature and based on calibration data
KR102634315B1 (ko) * 2016-05-11 2024-02-13 삼성전자주식회사 패리티 에러 검출 회로를 포함하는 메모리 장치
KR102684558B1 (ko) * 2016-12-28 2024-07-15 에스케이하이닉스 주식회사 반도체 장치 및 반도체 시스템
US11017834B2 (en) * 2018-11-30 2021-05-25 Micron Technology, Inc. Refresh command management

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US4792896A (en) * 1983-12-07 1988-12-20 516277 Ontario Limited Storage controller emulator providing transparent resource sharing in a computer system
JP2525765B2 (ja) 1985-12-26 1996-08-21 旭化成工業株式会社 電気発破装置
US4939692A (en) * 1988-09-15 1990-07-03 Intel Corporation Read-only memory for microprocessor systems having shared address/data lines
US4965828A (en) * 1989-04-05 1990-10-23 Quadri Corporation Non-volatile semiconductor memory with SCRAM hold cycle prior to SCRAM-to-E2 PROM backup transfer
US5127014A (en) * 1990-02-13 1992-06-30 Hewlett-Packard Company Dram on-chip error correction/detection
US5307314A (en) * 1991-07-15 1994-04-26 Micron Technology, Inc. Split read/write dynamic random access memory
US5729503A (en) * 1994-12-23 1998-03-17 Micron Technology, Inc. Address transition detection on a synchronous design
US5822334A (en) * 1996-01-05 1998-10-13 Unisys Corporation High speed initialization system for RAM devices using JTAG loop for providing valid parity bits
US5587961A (en) * 1996-02-16 1996-12-24 Micron Technology, Inc. Synchronous memory allowing early read command in write to read transitions
KR100364127B1 (ko) * 1997-12-29 2003-04-11 주식회사 하이닉스반도체 칩-세트
US6560669B1 (en) * 1998-05-19 2003-05-06 Micron Technology, Inc. Double data rate synchronous memory with block-write
US6233190B1 (en) * 1999-08-30 2001-05-15 Micron Technology, Inc. Method of storing a temperature threshold in an integrated circuit, method of modifying operation of dynamic random access memory in response to temperature, programmable temperature sensing circuit and memory integrated circuit
US6978367B1 (en) 1999-10-21 2005-12-20 International Business Machines Corporation Selective data encryption using style sheet processing for decryption by a client proxy
DE10108605C1 (de) * 2001-02-22 2002-05-29 Kostal Leopold Gmbh & Co Kg Elektrischer Schalter
US6788593B2 (en) * 2001-02-28 2004-09-07 Rambus, Inc. Asynchronous, high-bandwidth memory component using calibrated timing elements
EP1359547A3 (de) * 2002-03-29 2006-05-24 Koninklijke Philips Electronics N.V. Verfahren zur Digitalbildverarbeitung für Anwendungen mit niedriger Bitrate
JP2004015434A (ja) * 2002-06-06 2004-01-15 Elpida Memory Inc 多数決回路
US6809990B2 (en) * 2002-06-21 2004-10-26 Micron Technology, Inc. Delay locked loop control circuit
KR100546335B1 (ko) * 2003-07-03 2006-01-26 삼성전자주식회사 데이터 반전 스킴을 가지는 반도체 장치
US6961269B2 (en) * 2003-06-24 2005-11-01 Micron Technology, Inc. Memory device having data paths with multiple speeds
US7508722B2 (en) 2004-01-27 2009-03-24 Micron Technology, Inc. Memory device having strobe terminals with multiple functions

Also Published As

Publication number Publication date
US7944761B2 (en) 2011-05-17
US20090231936A1 (en) 2009-09-17
KR20060120262A (ko) 2006-11-24
DE602005001266T2 (de) 2008-01-24
US20050165999A1 (en) 2005-07-28
EP1709644B1 (de) 2007-05-30
CN1934651A (zh) 2007-03-21
JP4747342B2 (ja) 2011-08-17
TWI282097B (en) 2007-06-01
US20100265777A1 (en) 2010-10-21
CN101740106A (zh) 2010-06-16
ATE363715T1 (de) 2007-06-15
US7508722B2 (en) 2009-03-24
KR100779284B1 (ko) 2007-11-23
US7751260B2 (en) 2010-07-06
JP2007535083A (ja) 2007-11-29
EP1709644A1 (de) 2006-10-11
WO2005073974A1 (en) 2005-08-11
TW200539194A (en) 2005-12-01

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