EP1331539B1 - Sicherer Modus für Prozessoren, die Speicherverwaltung und Unterbrechungen unterstützen - Google Patents

Sicherer Modus für Prozessoren, die Speicherverwaltung und Unterbrechungen unterstützen Download PDF

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Publication number
EP1331539B1
EP1331539B1 EP02100727.3A EP02100727A EP1331539B1 EP 1331539 B1 EP1331539 B1 EP 1331539B1 EP 02100727 A EP02100727 A EP 02100727A EP 1331539 B1 EP1331539 B1 EP 1331539B1
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EP
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Prior art keywords
secure
instruction
activation sequence
security
sequence
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Expired - Lifetime
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EP02100727.3A
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English (en)
French (fr)
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EP1331539A2 (de
EP1331539A3 (de
Inventor
Franck Dahan
Christian Roussel
Alain Bruno Chateau
Peter Harry Cumming
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Texas Instruments France SAS
Texas Instruments Inc
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Texas Instruments France SAS
Texas Instruments Inc
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Priority to EP02100727.3A priority Critical patent/EP1331539B1/de
Priority to US10/256,642 priority patent/US7890753B2/en
Priority to US10/256,596 priority patent/US7120771B2/en
Priority to US10/256,523 priority patent/US7237081B2/en
Priority to EP02292912.9A priority patent/EP1329787B1/de
Priority to US10/322,893 priority patent/US8479022B2/en
Publication of EP1331539A2 publication Critical patent/EP1331539A2/de
Priority to JP2003419725A priority patent/JP2004199693A/ja
Publication of EP1331539A3 publication Critical patent/EP1331539A3/de
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Publication of EP1331539B1 publication Critical patent/EP1331539B1/de
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/50—Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems
    • G06F21/55—Detecting local intrusion or implementing counter-measures
    • G06F21/556—Detecting local intrusion or implementing counter-measures involving covert channels, i.e. data leakage between processes
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/14—Protection against unauthorised use of memory or access to memory
    • G06F12/1458—Protection against unauthorised use of memory or access to memory by checking the subject access rights
    • G06F12/1491—Protection against unauthorised use of memory or access to memory by checking the subject access rights in a hierarchical protection system, e.g. privilege levels, memory rings
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/50—Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems
    • G06F21/51—Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems at application loading time, e.g. accepting, rejecting, starting or inhibiting executable software based on integrity or source reliability
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/50—Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems
    • G06F21/52—Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems during program execution, e.g. stack integrity ; Preventing unwanted data erasure; Buffer overflow
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
    • G06F21/74—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information operating in dual or compartmented mode, i.e. at least one secure mode
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/82—Protecting input, output or interconnection devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
    • G06F9/30047—Prefetch instructions; cache control instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3802—Instruction prefetching
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/468—Specific access rights for resources, e.g. using capability register
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2221/00—Indexing scheme relating to security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F2221/21—Indexing scheme relating to G06F21/00 and subgroups addressing additional information or applications relating to security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F2221/2101—Auditing as a secondary aspect
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2221/00—Indexing scheme relating to security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F2221/21—Indexing scheme relating to G06F21/00 and subgroups addressing additional information or applications relating to security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F2221/2105—Dual mode as a secondary aspect
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2221/00—Indexing scheme relating to security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F2221/21—Indexing scheme relating to G06F21/00 and subgroups addressing additional information or applications relating to security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F2221/2141—Access rights, e.g. capability lists, access control lists, access tables, access matrices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2221/00—Indexing scheme relating to security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F2221/21—Indexing scheme relating to G06F21/00 and subgroups addressing additional information or applications relating to security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F2221/2143—Clearing memory, e.g. to prevent the data from being stolen
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2221/00—Indexing scheme relating to security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F2221/21—Indexing scheme relating to G06F21/00 and subgroups addressing additional information or applications relating to security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F2221/2149—Restricted operating environment
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2221/00—Indexing scheme relating to security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F2221/21—Indexing scheme relating to G06F21/00 and subgroups addressing additional information or applications relating to security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F2221/2153—Using hardware token as a secondary aspect

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Computer Security & Cryptography (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Mathematical Physics (AREA)
  • Storage Device Security (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Claims (13)

  1. Ein Verfahren zum Betrieben eines digitalen Systems mit einem Mechanismus für eine CPU (200) mit einem Befehlsausführungspipeline, um ein Sicherbetriebsmodus umzuschalten, welches Verfahren aus den folgenden Schritten besteht:
    das Springen in einer Einsprungsadresse (410) bei einer besonderen Adresse in einem Befehlsspeicher (311);
    die Ausführung einer Aktivierungssequenz (413) von Befehlen mit Anfang beim Einsprungsadresse (410);
    die Überwachung von vorbestimmten Signalen (330) innerhalb des Systems, und die Erkennung eines bestimmten Musters in den Signalen, die beim Ausführung der Aktivierungssequenz (413) erzeugt werden;
    und
    die Durchsetzung eines Sicherheitssignals (302) und das Umschalten des Sicherbetriebsmodus beim Erkennen des vordefinierten Musters.
  2. Das Verfahren nach Anspruch 1, wobei die CPU (200) einen Befehlscache (204) hat, und dazu bestehend aus dem Schritt von keinem Umschalten des Sicherbetriebsmodus, wenn die Aktivierungssequenz (413) mit Anfang bei einer Einsprungsadresse (410) in einem Befehlscache ausgeführt wird.
  3. Das Verfahren nach Anspruch 1, wobei der letzte nicht-vertrauenswürdig Befehl bevor die Ausführung der Aktivierungssequenz (413) entweder ein JUMP zur Einsprungsadresse-Befehl (410) oder ein bekannter Befehl ist.
  4. Das Verfahren nach jenen vorhergehenden Ansprüchen, wobei die Aktivierungssequenz (413) der Befehle länger als die Länge des Befehlsausführungspipelines der CPU (200).
  5. Das Verfahren nach jenen vorhergehenden Ansprüchen, wobei die CPU (200) einen Befehlscache (204) hat und wobei die Aktivierungssequenz (413) einen Befehlscache-Flush-Befehl einschließt, damit mindestens n-Befehle der Aktivierungssequenz (413) bevor die Entleerung des Befehlscaches (204) ausgeführt werden, wobei n die Befehlspipeline-Länge ist.
  6. Das Verfahren nach jenen vorhergehenden Ansprüchen, wobei die CPU (200) einen Befehlscache (204) hat, und wobei die Aktivierungssequenz (413) einen Befehlscache-Deaktivierungsbefehl einschließt, damit mindestens die Befehle der Aktivierungssequenz (413) bevor die Deaktivierung des Befehlscaches ausgeführt werden, wobei n die Befehlspipeline-Länge ist.
  7. Das Verfahren nach Ansprüchen 5 oder 6, wobei der Flush-Befehl oder Deaktivierungsbefehl in der Aktivierungssequenz (413) befindet, damit seine Adresse der Position-P in einer Linie des Befehlscaches (204) entspricht, wobei die Distanz zwischen p und dem letzten Befehl einer Linie in dem Befehlscache (204) dem Rang der Ausführungsstufe in dem CPU-Pipeline entspricht.
  8. Das Verfahren nach jenen vorhergehenden Ansprüchen, wobei der letzte Befehl der Aktivierungssequenz (413) einen Verzweigungsbefehl ist, und wobei alle anderen Befehle in der Aktivierungssequenz (413) NOP-Befehle außer eines Cache-Flush-Befehls (710) oder eines Cachedeaktivierungsbefehls sind.
  9. Das Verfahren nach jenen vorhergehenden Ansprüchen, wobei der Schritt der Schritten sind:
    die Überwachung eines Sets von einem oder mehreren Zustandssignalen (325, 327, 331, 333), die durch die CPU und das System während jedes Zugriffs der Aktivierungssequenz (413) geliefert werden;
    das Abbrechen der Aktivierungssequenz (413), wenn die Zustandssignale (325, 327, 331, 333) zeigen, dass jener der Aktivierungssequenzzugriffe keinen Befehls-Fetch-Zugriff ist.
  10. Das Verfahren nach Anspruch 9, dazu bestehend aus den Schritt von:
    dem Abbrechen der Aktivierungssequenz (413), wenn die Zustandssignale (333) zeigen, dass ein Datenzugriff während der Ausführung der Aktivierungssequenz (413) ausgeführt wird.
  11. Das Verfahren nach Ansprüchen 9 - 10, dazu bestehend aus dem Schritt von dem Abbrechen der Aktivierungssequenz (413), wenn die Zustandssignale (325) zeigen, dass die Störungen nicht verhindert sind, oder wenn die Zustandssignale (331) zeigen, dass jener der Aktivierungssequenzzugriffe im Cache speichbar ist, oder wenn die Zustandssignale zeigen, dass eine vorbestimmte Synchronisationssequenz während der Ausführung der Aktivierungssequenz (413) nicht gefolgt wird.
  12. Das Verfahren nach jenen vorhergehenden Ansprüchen dazu bestehend aus den Schritten von:
    der Festlegung (502) eines Betriebsmodus nach vordefiniertem Sicherheitskriterium durch das Aufrufen eines OS-Task-Manager bevor Springen zur Einsprungsadresse (410);
    nach dem Eintritt des Sicherbetriebsmodus (620), die Festlegung (526) einer Umgebung, die für Sichercode-Ausführung durch die Ausführung einer Vielzahl von Befehlen (414) von einem sicheren Nur-Lese-Speicher (310) geeignet ist;
    der Ausführung (528) einer sicheren Routine (416) von dem sicheren Nur-Lese-Speicher (310);
    dem Realisieren einer Ausgangssequenz (418) von dem sicheren Nur-Lese-Speicher (310);
    dem Springen (530) zu einem Ausgangspunkt in einem veröffentlichen Nur-Lese-Speicher (311).
  13. Ein digitales System, bestehend aus:
    einer CPU (200) mit einem Befehlsausführungs-Pipeline;
    einem veröffentlichen Nur-Lese-Speicher (311), der mit einem Befehls-Bus (330) der CPU (200) zum Halten von unsicheren Befehlen verbunden ist, der veröffentliche Nur-Lese-Speicher (311) seiend immer durch die CPU (200) zugriffbar;
    einem sicheren Nur-Lese-Speicher (310), der mit dem Befehls-Bus (330) der CPU (200) zum Halten von sicheren Befehlen verbunden ist, der sichere Nur-Lese-Speicher (310) seiend zugriffbar nur wenn ein Sicherheitssignal festgelegt wird;
    einer Sicherheits-Zustands-Maschine (300) verbunden mit der CPU (200) zur Überwachung eines Sets von Zustandssignalen (325, 327, 331, 333) und verbunden mit dem Befehls-Adresse-Bus (300) zur Überwachung der Befehls-Adresse-Signale, die Sicherheitszustandsmaschine (300) habend einen Ausgang zur Festlegung des Sicherheitssignals (302), wenn ein Sicherbetriebsmodus festgelegt wird;
    einer Sicherheitsressource (310, 312, 316a, 316b) verbunden mit der CPU (200), dass durch die CPU zugriffbar ist, nur wenn das Sicherheitssignal (302) durchgesetzt ist; und
    wobei die Sicherheitszustandsmaschine (300) betriebsfähig ist, die vorbestimmten Signale innerhalb des Systems überzuwachen, um einen vordefinierten Muster in den Signalen zu erkennen, welche Signale beim Ausführen der Aktivierungssequenz von Befehlen (413) in einem veröffentlichen Nur-Lese-Speicher (311) erzeugt werden, und um ein Sicherheitssignal (302) festzulegen und das Sicherbetriebsmodus beim Erkennen des jeweiligen vordefinierten Musters einzugehen.
EP02100727.3A 2002-01-16 2002-06-20 Sicherer Modus für Prozessoren, die Speicherverwaltung und Unterbrechungen unterstützen Expired - Lifetime EP1331539B1 (de)

Priority Applications (7)

Application Number Priority Date Filing Date Title
EP02100727.3A EP1331539B1 (de) 2002-01-16 2002-06-20 Sicherer Modus für Prozessoren, die Speicherverwaltung und Unterbrechungen unterstützen
US10/256,596 US7120771B2 (en) 2002-01-16 2002-09-27 Secure mode for processors supporting MMU
US10/256,523 US7237081B2 (en) 2002-01-16 2002-09-27 Secure mode for processors supporting interrupts
US10/256,642 US7890753B2 (en) 2002-01-16 2002-09-27 Secure mode for processors supporting MMU and interrupts
EP02292912.9A EP1329787B1 (de) 2002-01-16 2002-11-25 Anzeige des sicheren Moduses für intelligente Telefone und persönliche digitale Assistenten
US10/322,893 US8479022B2 (en) 2002-01-16 2002-12-18 Secure mode indicator for smart phone or PDA
JP2003419725A JP2004199693A (ja) 2002-01-16 2003-12-17 高度機能電話または携帯情報端末用機密保護モード指示器

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
EP02290115 2002-01-16
EP02290115 2002-01-16
EP02100727.3A EP1331539B1 (de) 2002-01-16 2002-06-20 Sicherer Modus für Prozessoren, die Speicherverwaltung und Unterbrechungen unterstützen

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EP1331539A2 EP1331539A2 (de) 2003-07-30
EP1331539A3 EP1331539A3 (de) 2008-10-22
EP1331539B1 true EP1331539B1 (de) 2016-09-28

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