DE69321207D1 - Abtastprüfung für integrierte Schaltkreise - Google Patents
Abtastprüfung für integrierte SchaltkreiseInfo
- Publication number
- DE69321207D1 DE69321207D1 DE69321207T DE69321207T DE69321207D1 DE 69321207 D1 DE69321207 D1 DE 69321207D1 DE 69321207 T DE69321207 T DE 69321207T DE 69321207 T DE69321207 T DE 69321207T DE 69321207 D1 DE69321207 D1 DE 69321207D1
- Authority
- DE
- Germany
- Prior art keywords
- scan
- test
- data
- integrated circuits
- cell
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000012360 testing method Methods 0.000 title abstract 9
- 238000000034 method Methods 0.000 abstract 3
- 230000000644 propagated effect Effects 0.000 abstract 1
- 230000001902 propagating effect Effects 0.000 abstract 1
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318541—Scan latches or cell details
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Tests Of Electronic Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US07/995,754 US5450418A (en) | 1992-12-23 | 1992-12-23 | Pseudo master slave capture mechanism for scan elements |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69321207D1 true DE69321207D1 (de) | 1998-10-29 |
DE69321207T2 DE69321207T2 (de) | 1999-05-20 |
Family
ID=25542173
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69321207T Expired - Fee Related DE69321207T2 (de) | 1992-12-23 | 1993-11-30 | Abtastprüfung für integrierte Schaltkreise |
Country Status (4)
Country | Link |
---|---|
US (1) | US5450418A (de) |
EP (1) | EP0604032B1 (de) |
JP (1) | JPH06230088A (de) |
DE (1) | DE69321207T2 (de) |
Families Citing this family (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5572536A (en) * | 1994-05-26 | 1996-11-05 | Texas Instruments Incorporated | Digital circuitry with improved parallel signature analysis capability |
US5732091A (en) * | 1994-11-21 | 1998-03-24 | Texas Instruments Incorporated | Self initializing and correcting shared resource boundary scan with output latching |
US5715255A (en) * | 1994-11-21 | 1998-02-03 | Texas Instruments Incorporated | Low overhead memory designs for IC terminals |
US5715254A (en) * | 1994-11-21 | 1998-02-03 | Texas Instruments Incorporated | Very low overhead shared resource boundary scan design |
US5701307A (en) * | 1994-12-16 | 1997-12-23 | Texas Instruments Incorporated | Low overhead input and output boundary scan cells |
US5706296A (en) * | 1995-02-28 | 1998-01-06 | Texas Instruments Incorporated | Bi-directional scan design with memory and latching circuitry |
US5938783A (en) * | 1995-04-28 | 1999-08-17 | Texas Instruments Incorporated | Dual mode memory for IC terminals |
US5880595A (en) * | 1995-04-28 | 1999-03-09 | Texas Instruments Incorporated | IC having memoried terminals and zero-delay boundary scan |
US5656953A (en) * | 1995-05-31 | 1997-08-12 | Texas Instruments Incorporated | Low overhead memory designs for IC terminals |
KR19990082339A (ko) * | 1996-02-06 | 1999-11-25 | 크리스티안 웬너호름, 괴란 놀드런드흐 | 집적된 회로 장치 시험용 어셈블리 및 방법 |
US5951702A (en) * | 1997-04-04 | 1999-09-14 | S3 Incorporated | RAM-like test structure superimposed over rows of macrocells with added differential pass transistors in a CPU |
US6145104A (en) * | 1998-02-12 | 2000-11-07 | Motorola, Inc. | Data processing system external pin connectivity to complex functions |
US6405335B1 (en) | 1998-02-25 | 2002-06-11 | Texas Instruments Incorporated | Position independent testing of circuits |
US6728915B2 (en) | 2000-01-10 | 2004-04-27 | Texas Instruments Incorporated | IC with shared scan cells selectively connected in scan path |
US6769080B2 (en) | 2000-03-09 | 2004-07-27 | Texas Instruments Incorporated | Scan circuit low power adapter with counter |
US6510534B1 (en) * | 2000-06-29 | 2003-01-21 | Logicvision, Inc. | Method and apparatus for testing high performance circuits |
JP4305871B2 (ja) * | 2003-09-08 | 2009-07-29 | 富士通株式会社 | レジスタファイル及びその記憶素子 |
US7447961B2 (en) * | 2004-07-29 | 2008-11-04 | Marvell International Ltd. | Inversion of scan clock for scan cells |
JP6988156B2 (ja) * | 2017-05-11 | 2022-01-05 | 富士通株式会社 | 診断回路及び診断回路の制御方法 |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4051352A (en) * | 1976-06-30 | 1977-09-27 | International Business Machines Corporation | Level sensitive embedded array logic system |
JP2945103B2 (ja) * | 1990-05-15 | 1999-09-06 | 株式会社リコー | テスト用スキャン回路装置 |
US5210759A (en) * | 1990-11-19 | 1993-05-11 | Motorola, Inc. | Data processing system having scan testing using set latches for selectively observing test data |
US5271019A (en) * | 1991-03-15 | 1993-12-14 | Amdahl Corporation | Scannable system with addressable scan reset groups |
-
1992
- 1992-12-23 US US07/995,754 patent/US5450418A/en not_active Expired - Fee Related
-
1993
- 1993-11-30 EP EP93309527A patent/EP0604032B1/de not_active Expired - Lifetime
- 1993-11-30 DE DE69321207T patent/DE69321207T2/de not_active Expired - Fee Related
- 1993-12-10 JP JP5310061A patent/JPH06230088A/ja not_active Withdrawn
Also Published As
Publication number | Publication date |
---|---|
EP0604032A3 (en) | 1994-08-24 |
US5450418A (en) | 1995-09-12 |
EP0604032A2 (de) | 1994-06-29 |
EP0604032B1 (de) | 1998-09-23 |
JPH06230088A (ja) | 1994-08-19 |
DE69321207T2 (de) | 1999-05-20 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
DE69321207T2 (de) | Abtastprüfung für integrierte Schaltkreise | |
US4698830A (en) | Shift register latch arrangement for enhanced testability in differential cascode voltage switch circuit | |
GB9127379D0 (en) | An implementation of the ieee 1149.1 boundary-scan architecture | |
IT1230685B (it) | Collaudo di circuiti integrati presenti su un supporto | |
EP0358365A3 (de) | Prüf-Puffer/Register | |
DE69127060T2 (de) | Tester für integrierte Schaltungen | |
DE69429741D1 (de) | Analoge, selbstständige Prüfbusstruktur zum Testen integrierter Schaltungen auf einer gedruckten Leiterplatte | |
DE60228551D1 (de) | Mehrfacherfassungs-dft-system für integrierte schaltungen auf scan-basis | |
DE69830521D1 (de) | Automatisches Schaltkreisprüfgerät für Halbleitervorrichtungen | |
GB1416786A (en) | Method of testing an integrated circuit block | |
BR7906298A (pt) | Metodo e disposicao para teste de circuitos sequenciais representados por circuitos monoliticamente integrados de semi-condutores | |
KR880014475A (ko) | 반도체 집적회로장치 | |
DE69323681T2 (de) | Stressprüfung für Speichernetzwerke in integrierten Schaltungen | |
EP0367710A3 (de) | Diagnostika einer Leiterplatte mit einer Mehrzahl elektronischer Hybridbauelemente | |
US4428060A (en) | Shift register latch circuit means for check and test purposes and contained in LSI circuitry conforming to level sensitive scan design (LSSD) rules and techniques | |
DE69317221D1 (de) | Abtastprüfung für integrierte Schaltungen | |
KR880003248A (ko) | 반도체 집적회로장치 | |
ES8609738A1 (es) | Una instalacion para comprobar circuitos electronicos fun- cionales | |
EP0428465A3 (en) | Method and apparatus for detecting oscillator stuck faults in a level sensitive scan design (lssd) system | |
DE3681666D1 (de) | Integrierter halbleiterspeicher. | |
DE69226401D1 (de) | Ausführung der IEEE 1149.1-Schnittstellenarchitektur | |
DE69833123D1 (de) | Schaltungsanordnung zum testen eines kerns | |
EP0358371A3 (de) | Erweiterte Prüfschaltung | |
DE60223043D1 (de) | Elektronischer schaltkreis und testverfahren | |
ATE146282T1 (de) | Platine mit eingebauter kontaktfühlerprüfung für integrierte schaltungen |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |