MXPA03002064A - Arreglo de circuito y procedimiento para detectar un ataque indeseado en un circuito integrado. - Google Patents

Arreglo de circuito y procedimiento para detectar un ataque indeseado en un circuito integrado.

Info

Publication number
MXPA03002064A
MXPA03002064A MXPA03002064A MXPA03002064A MXPA03002064A MX PA03002064 A MXPA03002064 A MX PA03002064A MX PA03002064 A MXPA03002064 A MX PA03002064A MX PA03002064 A MXPA03002064 A MX PA03002064A MX PA03002064 A MXPA03002064 A MX PA03002064A
Authority
MX
Mexico
Prior art keywords
circuit
integrated circuit
detecting
signal line
line
Prior art date
Application number
MXPA03002064A
Other languages
English (en)
Inventor
Berndt Gammel
Original Assignee
Infineon Technologies Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Ag filed Critical Infineon Technologies Ag
Publication of MXPA03002064A publication Critical patent/MXPA03002064A/es

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/57—Protection from inspection, reverse engineering or tampering
    • H01L23/576—Protection from inspection, reverse engineering or tampering using active circuits
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31719—Security aspects, e.g. preventing unauthorised access during test
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Manipulation Of Pulses (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Dc Digital Transmission (AREA)
  • Noise Elimination (AREA)
MXPA03002064A 2000-09-11 2001-08-30 Arreglo de circuito y procedimiento para detectar un ataque indeseado en un circuito integrado. MXPA03002064A (es)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE10044837A DE10044837C1 (de) 2000-09-11 2000-09-11 Schaltungsanordnung und Verfahren zum Detektieren eines unerwünschten Angriffs auf eine integrierte Schaltung
PCT/DE2001/003335 WO2002021241A2 (de) 2000-09-11 2001-08-30 Schaltungsanordnung und verfahren zum detektieren eines unerwünschten angriffs auf eine integrierte schaltung

Publications (1)

Publication Number Publication Date
MXPA03002064A true MXPA03002064A (es) 2003-10-06

Family

ID=7655776

Family Applications (1)

Application Number Title Priority Date Filing Date
MXPA03002064A MXPA03002064A (es) 2000-09-11 2001-08-30 Arreglo de circuito y procedimiento para detectar un ataque indeseado en un circuito integrado.

Country Status (13)

Country Link
US (1) US7106091B2 (es)
EP (1) EP1334416B1 (es)
JP (1) JP4094944B2 (es)
KR (1) KR100508891B1 (es)
CN (1) CN1199092C (es)
AT (1) ATE293806T1 (es)
BR (1) BR0113810A (es)
DE (2) DE10044837C1 (es)
MX (1) MXPA03002064A (es)
RU (1) RU2251724C2 (es)
TW (1) TW539935B (es)
UA (1) UA72342C2 (es)
WO (1) WO2002021241A2 (es)

Families Citing this family (36)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10155802B4 (de) * 2001-11-14 2006-03-02 Infineon Technologies Ag Halbleiterchip mit FIB-Schutz
DE10221657A1 (de) * 2002-05-15 2003-11-27 Infineon Technologies Ag Informationsmatrix
DE10254658A1 (de) * 2002-11-22 2004-06-03 Philips Intellectual Property & Standards Gmbh Mikrocontroller und zugeordnetes Verfahren zum Abarbeiten der Programmierung des Mikrocontrollers
DE10324049B4 (de) * 2003-05-27 2006-10-26 Infineon Technologies Ag Integrierte Schaltung und Verfahren zum Betreiben der integrierten Schaltung
DE10345240A1 (de) * 2003-09-29 2005-05-04 Infineon Technologies Ag Integrierte Schaltung mit Strahlungssensoranordnung
DE10347301B4 (de) 2003-10-08 2007-12-13 Infineon Technologies Ag Schaltung mit einem Bus mit mehreren Empfängern
FR2865828A1 (fr) * 2004-01-29 2005-08-05 St Microelectronics Sa Procede de securisation du mode de test d'un circuit integre par detection d'intrusion
FR2865827A1 (fr) * 2004-01-29 2005-08-05 St Microelectronics Sa Securisation du mode de test d'un circuit integre
EP1721231B1 (en) * 2004-02-24 2009-12-23 Nxp B.V. Method and apparatus for protecting an integrated circuit using an intrusion detection by Monte Carlo analysis
DE102004014435A1 (de) * 2004-03-24 2005-11-17 Siemens Ag Anordnung mit einem integrierten Schaltkreis
DE102004020576B4 (de) * 2004-04-27 2007-03-15 Infineon Technologies Ag Datenverarbeitungsvorrichtung mit schaltbarer Ladungsneutralität und Verfahren zum Betreiben einer Dual-Rail-Schaltungskomponente
JP4815141B2 (ja) * 2005-03-29 2011-11-16 富士通株式会社 回路異常動作検出システム
FR2885417A1 (fr) * 2005-05-04 2006-11-10 St Microelectronics Sa Circuit integre comportant un mode de test securise par detection de l'etat chaine des cellules configurables du circuit integre
FR2888330B1 (fr) * 2005-07-08 2007-10-05 St Microelectronics Sa Circuit integre comportant un mode de test securise par detection de l'etat d'un signal de commande
US7577886B2 (en) 2005-07-08 2009-08-18 Stmicroelectronics, Sa Method for testing an electronic circuit comprising a test mode secured by the use of a signature, and associated electronic circuit
US7881465B2 (en) * 2005-08-08 2011-02-01 Infineon Technologies Ag Circuit and method for calculating a logic combination of two encrypted input operands
DE102005037357B3 (de) * 2005-08-08 2007-02-01 Infineon Technologies Ag Logikschaltung und Verfahren zum Berechnen eines maskierten Ergebnisoperanden
DE102005042790B4 (de) 2005-09-08 2010-11-18 Infineon Technologies Ag Integrierte Schaltungsanordnung und Verfahren zum Betrieb einer solchen
FR2897439A1 (fr) * 2006-02-15 2007-08-17 St Microelectronics Sa Circuit elelctronique comprenant un mode de test securise par l'utilisation d'un identifiant, et procede associe
DE102007010771A1 (de) * 2007-03-06 2008-10-30 Robert Bosch Gmbh Verfahren zur Bestimmung einer asymmetrischen Signalverzögerung eines Signalpfades innerhalb einer integrierten Schaltung
KR101299602B1 (ko) 2007-03-27 2013-08-26 삼성전자주식회사 리버스 엔지니어링을 보호하는 집적회로
US8188860B2 (en) 2007-10-22 2012-05-29 Infineon Technologies Ag Secure sensor/actuator systems
US8195995B2 (en) * 2008-07-02 2012-06-05 Infineon Technologies Ag Integrated circuit and method of protecting a circuit part of an integrated circuit
DE102008036422A1 (de) * 2008-08-05 2010-02-11 Infineon Technologies Ag Halbleiter-Chip mit Prüfeinrichtung
FR2935059B1 (fr) * 2008-08-12 2012-05-11 Groupe Des Ecoles De Telecommunications Get Ecole Nationale Superieure Des Telecommunications Enst Procede de detection d'anomalies dans un circuit de cryptographie protege par logique differentielle et circuit mettant en oeuvre un tel procede
FR2938953B1 (fr) * 2008-11-21 2011-03-11 Innova Card Dispositif de protection d'un boitier de circuit integre electronique contre les intrusions par voie physique ou chimique.
FR2949163B1 (fr) * 2009-08-12 2011-12-09 St Microelectronics Rousset Surveillance de l'activite d'un circuit electronique
US8874926B1 (en) * 2012-03-08 2014-10-28 Sandia Corporation Increasing security in inter-chip communication
JP5954872B2 (ja) * 2012-09-20 2016-07-20 ルネサスエレクトロニクス株式会社 半導体集積回路
CN103035077A (zh) 2012-11-29 2013-04-10 深圳市新国都技术股份有限公司 一种pos机数据信息保护电路
US9397666B2 (en) * 2014-07-22 2016-07-19 Winbond Electronics Corporation Fault protection for clock tree circuitry
EP2983102A1 (en) 2014-08-07 2016-02-10 EM Microelectronic-Marin SA Integrated circuit with distributed clock tampering detectors
EP3147830B1 (en) 2015-09-23 2020-11-18 Nxp B.V. Protecting an integrated circuit
FR3054344B1 (fr) * 2016-07-25 2018-09-07 Tiempo Circuit integre protege.
US10547461B2 (en) 2017-03-07 2020-01-28 Nxp B.V. Method and apparatus for binding stacked die using a physically unclonable function
US10839109B2 (en) 2018-11-14 2020-11-17 Massachusetts Institute Of Technology Integrated circuit (IC) portholes and related techniques

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4933898A (en) * 1989-01-12 1990-06-12 General Instrument Corporation Secure integrated circuit chip with conductive shield
US5027397A (en) 1989-09-12 1991-06-25 International Business Machines Corporation Data protection by detection of intrusion into electronic assemblies
JPH0438793A (ja) * 1990-06-04 1992-02-07 Toshiba Corp データ転送制御回路およびこれを用いたダイナミック型半導体記憶装置
RU2106686C1 (ru) 1993-06-24 1998-03-10 Владимир Владимирович Волга Способ защиты от обращений к памяти эвм посторонних пользователей и устройство для его осуществления
US5377264A (en) * 1993-12-09 1994-12-27 Pitney Bowes Inc. Memory access protection circuit with encryption key
US5825878A (en) * 1996-09-20 1998-10-20 Vlsi Technology, Inc. Secure memory management unit for microprocessor
US5861662A (en) 1997-02-24 1999-01-19 General Instrument Corporation Anti-tamper bond wire shield for an integrated circuit
US6381692B1 (en) * 1997-07-16 2002-04-30 California Institute Of Technology Pipelined asynchronous processing
ES2270623T3 (es) 1998-11-05 2007-04-01 Infineon Technologies Ag Circuito de proteccion para un circuito integrado.

Also Published As

Publication number Publication date
US7106091B2 (en) 2006-09-12
EP1334416A2 (de) 2003-08-13
EP1334416B1 (de) 2005-04-20
ATE293806T1 (de) 2005-05-15
KR20030032016A (ko) 2003-04-23
WO2002021241A3 (de) 2003-06-05
DE50105977D1 (de) 2005-05-25
BR0113810A (pt) 2004-01-13
KR100508891B1 (ko) 2005-08-18
RU2251724C2 (ru) 2005-05-10
US20030218475A1 (en) 2003-11-27
JP2004508630A (ja) 2004-03-18
WO2002021241A2 (de) 2002-03-14
JP4094944B2 (ja) 2008-06-04
TW539935B (en) 2003-07-01
CN1460203A (zh) 2003-12-03
UA72342C2 (en) 2005-02-15
DE10044837C1 (de) 2001-09-13
CN1199092C (zh) 2005-04-27

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