PL351223A1 - Integrated circuit testing method - Google Patents

Integrated circuit testing method

Info

Publication number
PL351223A1
PL351223A1 PL01351223A PL35122301A PL351223A1 PL 351223 A1 PL351223 A1 PL 351223A1 PL 01351223 A PL01351223 A PL 01351223A PL 35122301 A PL35122301 A PL 35122301A PL 351223 A1 PL351223 A1 PL 351223A1
Authority
PL
Poland
Prior art keywords
integrated circuit
signal output
test mode
testing method
test
Prior art date
Application number
PL01351223A
Other versions
PL197810B1 (en
Inventor
Matthias Eichin
Alexander Kurz
Original Assignee
Vishay Semiconductor Gmbh
Atmel Germany Gmbh
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Vishay Semiconductor Gmbh, Atmel Germany Gmbh filed Critical Vishay Semiconductor Gmbh
Publication of PL351223A1 publication Critical patent/PL351223A1/en
Publication of PL197810B1 publication Critical patent/PL197810B1/en

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/48—Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/46—Test trigger logic

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Sampling And Sample Adjustment (AREA)
  • Investigating Or Analyzing Materials By The Use Of Electric Means (AREA)

Abstract

Created by a passive resistor (W1,W2), a potential value at a signal output (OUT) causes a switchover into a test mode when a test signal (SW1,SW2) is coupled to the signal output and a circuit device (SCH) generates test signals by applying defined potential values. In a first preset time period the potential at the signal output is compared with preset reference values. In a second time period the integrated circuit (IC) is switched over into a test mode. An Independent claim is also included for a circuit structure for switching over the method of the present invention into a test mode.
PL351223A 2000-12-22 2001-12-17 Method of testing integrated circuit and circuit arrangement PL197810B1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE10064478A DE10064478B4 (en) 2000-12-22 2000-12-22 Method for testing an integrated circuit and circuit arrangement

Publications (2)

Publication Number Publication Date
PL351223A1 true PL351223A1 (en) 2002-07-01
PL197810B1 PL197810B1 (en) 2008-04-30

Family

ID=7668594

Family Applications (1)

Application Number Title Priority Date Filing Date
PL351223A PL197810B1 (en) 2000-12-22 2001-12-17 Method of testing integrated circuit and circuit arrangement

Country Status (10)

Country Link
US (2) US6937048B2 (en)
EP (1) EP1217630B1 (en)
JP (1) JP3999512B2 (en)
KR (1) KR20020051831A (en)
CN (1) CN1189891C (en)
AT (1) ATE460736T1 (en)
DE (2) DE10064478B4 (en)
HK (1) HK1048158A1 (en)
PL (1) PL197810B1 (en)
TW (1) TW584734B (en)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10353586A1 (en) * 2003-11-17 2005-06-30 Infineon Technologies Ag An input / output switching arrangement for semiconductor circuits and method for testing driver circuits of semiconductor circuits
US7272763B2 (en) * 2004-09-30 2007-09-18 Lsi Corporation Built-in self test circuitry for process monitor circuit for rapidchip and ASIC devices
DE102005029495A1 (en) * 2005-06-24 2006-12-28 Texas Instruments Deutschland Gmbh Integrated power circuit for e.g. measuring on-state resistance of MOSFET, has power component with ports, and internal switch connecting ports of MOSFET with one internal circuit point that is connected with one external circuit point
DE102005052269A1 (en) 2005-10-27 2007-05-10 Atmel Germany Gmbh Integrated circuit with integrated test help subcircuit
JP4967395B2 (en) * 2006-03-22 2012-07-04 富士電機株式会社 Semiconductor integrated circuit
KR20090036395A (en) * 2007-10-09 2009-04-14 주식회사 하이닉스반도체 Circuit for cognizance of reference voltage of semiconductor memory apparatus
US7724014B2 (en) * 2008-02-15 2010-05-25 Texas Instruments Incorporated On-chip servo loop integrated circuit system test circuitry and method
JP4748181B2 (en) * 2008-05-07 2011-08-17 日本テキサス・インスツルメンツ株式会社 Semiconductor device test apparatus and test method
KR101647302B1 (en) * 2009-11-26 2016-08-10 삼성전자주식회사 Probe card and test apparatus having the same
ITMI20111418A1 (en) 2011-07-28 2013-01-29 St Microelectronics Srl TESTING ARCHITECTURE OF CIRCUITS INTEGRATED ON A WAFER
TWI445986B (en) * 2012-04-02 2014-07-21 Mas Automation Corp Test system
DE102012013072B4 (en) 2012-07-02 2015-01-08 Micronas Gmbh Device for evaluating a magnetic field
DE102018200723A1 (en) * 2018-01-17 2019-07-18 Robert Bosch Gmbh Electrical circuit for testing primary internal signals of an ASIC
CN110579701A (en) * 2019-09-16 2019-12-17 晶晨半导体(上海)股份有限公司 Method for detecting pin connectivity of integrated chip
CN111426869B (en) * 2020-04-24 2023-08-22 西安紫光国芯半导体有限公司 Integrated circuit current detection device and method

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62170094A (en) 1986-01-21 1987-07-27 Mitsubishi Electric Corp Semiconductor storage circuit
JPH0389182A (en) * 1989-08-31 1991-04-15 Sharp Corp Integrated circuit apparatus
US5363383A (en) * 1991-01-11 1994-11-08 Zilog, Inc. Circuit for generating a mode control signal
KR930009490B1 (en) * 1991-07-15 1993-10-04 금성일렉트론 주식회사 Instantaneous test mode designation circuit
JP2827062B2 (en) * 1991-09-04 1998-11-18 シャープ株式会社 Integrated circuit
US5212442A (en) * 1992-03-20 1993-05-18 Micron Technology, Inc. Forced substrate test mode for packaged integrated circuits
US5847561A (en) * 1994-12-16 1998-12-08 Texas Instruments Incorporated Low overhead input and output boundary scan cells
US5568435A (en) * 1995-04-12 1996-10-22 Micron Technology, Inc. Circuit for SRAM test mode isolated bitline modulation
US5627478A (en) * 1995-07-06 1997-05-06 Micron Technology, Inc. Apparatus for disabling and re-enabling access to IC test functions
US6037792A (en) * 1996-12-21 2000-03-14 Stmicroelectronics, Inc. Burn-in stress test mode
DE19735406A1 (en) * 1997-08-14 1999-02-18 Siemens Ag Semiconductor component and method for testing and operating a semiconductor component
US6265889B1 (en) * 1997-09-30 2001-07-24 Kabushiki Kaisha Toshiba Semiconductor test circuit and a method for testing a semiconductor liquid crystal display circuit
KR100238256B1 (en) * 1997-12-03 2000-01-15 윤종용 Memory device using direct access mode test and test method thereof
US5933378A (en) * 1998-02-26 1999-08-03 Micron Technology, Inc. Integrated circuit having forced substrate test mode with improved substrate isolation

Also Published As

Publication number Publication date
EP1217630A3 (en) 2005-06-08
US20020079916A1 (en) 2002-06-27
US6937051B2 (en) 2005-08-30
DE10064478B4 (en) 2005-02-24
JP2002228726A (en) 2002-08-14
JP3999512B2 (en) 2007-10-31
CN1189891C (en) 2005-02-16
HK1048158A1 (en) 2003-03-21
DE10064478A1 (en) 2002-07-04
KR20020051831A (en) 2002-06-29
ATE460736T1 (en) 2010-03-15
DE50115381D1 (en) 2010-04-22
US6937048B2 (en) 2005-08-30
US20040239363A1 (en) 2004-12-02
CN1363841A (en) 2002-08-14
EP1217630A2 (en) 2002-06-26
PL197810B1 (en) 2008-04-30
EP1217630B1 (en) 2010-03-10
TW584734B (en) 2004-04-21

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Legal Events

Date Code Title Description
LAPS Decisions on the lapse of the protection rights

Effective date: 20131217