DE4111104C1 - - Google Patents

Info

Publication number
DE4111104C1
DE4111104C1 DE4111104A DE4111104A DE4111104C1 DE 4111104 C1 DE4111104 C1 DE 4111104C1 DE 4111104 A DE4111104 A DE 4111104A DE 4111104 A DE4111104 A DE 4111104A DE 4111104 C1 DE4111104 C1 DE 4111104C1
Authority
DE
Germany
Prior art keywords
transistors
bit line
bit
transistor
lines
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE4111104A
Other languages
German (de)
English (en)
Inventor
Roland Dipl.-Ing. 8000 Muenchen De Pfeiffer
Kurt Dr. 8028 Taufkirchen De Hoffmann
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Priority to DE4111104A priority Critical patent/DE4111104C1/de
Priority to DE59209399T priority patent/DE59209399D1/de
Priority to EP92105811A priority patent/EP0507336B1/de
Priority to AT92105811T priority patent/ATE168213T1/de
Application granted granted Critical
Publication of DE4111104C1 publication Critical patent/DE4111104C1/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/062—Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/065—Differential amplifiers of latching type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1048—Data bus control circuits, e.g. precharging, presetting, equalising

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Databases & Information Systems (AREA)
  • Static Random-Access Memory (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Dram (AREA)
  • Amplifiers (AREA)
  • Magnetic Record Carriers (AREA)
  • Holo Graphy (AREA)
DE4111104A 1991-04-05 1991-04-05 Expired - Fee Related DE4111104C1 (enExample)

Priority Applications (4)

Application Number Priority Date Filing Date Title
DE4111104A DE4111104C1 (enExample) 1991-04-05 1991-04-05
DE59209399T DE59209399D1 (de) 1991-04-05 1992-04-03 Dekodierte Ausleseschaltung
EP92105811A EP0507336B1 (de) 1991-04-05 1992-04-03 Dekodierte Ausleseschaltung
AT92105811T ATE168213T1 (de) 1991-04-05 1992-04-03 Dekodierte ausleseschaltung

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE4111104A DE4111104C1 (enExample) 1991-04-05 1991-04-05

Publications (1)

Publication Number Publication Date
DE4111104C1 true DE4111104C1 (enExample) 1992-10-01

Family

ID=6428913

Family Applications (2)

Application Number Title Priority Date Filing Date
DE4111104A Expired - Fee Related DE4111104C1 (enExample) 1991-04-05 1991-04-05
DE59209399T Expired - Fee Related DE59209399D1 (de) 1991-04-05 1992-04-03 Dekodierte Ausleseschaltung

Family Applications After (1)

Application Number Title Priority Date Filing Date
DE59209399T Expired - Fee Related DE59209399D1 (de) 1991-04-05 1992-04-03 Dekodierte Ausleseschaltung

Country Status (3)

Country Link
EP (1) EP0507336B1 (enExample)
AT (1) ATE168213T1 (enExample)
DE (2) DE4111104C1 (enExample)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4751681A (en) * 1985-08-23 1988-06-14 Texas Instruments Incorporated Dynamic differential amplifier
US4954992A (en) * 1987-12-24 1990-09-04 Mitsubishi Denki Kabushiki Kaisha Random access memory having separate read out and write in bus lines for reduced access time and operating method therefor

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3953839A (en) * 1975-04-10 1976-04-27 International Business Machines Corporation Bit circuitry for enhance-deplete ram
JPS5755592A (en) * 1980-09-18 1982-04-02 Nec Corp Memory device
US4649516A (en) * 1984-06-01 1987-03-10 International Business Machines Corp. Dynamic row buffer circuit for DRAM

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4751681A (en) * 1985-08-23 1988-06-14 Texas Instruments Incorporated Dynamic differential amplifier
US4954992A (en) * 1987-12-24 1990-09-04 Mitsubishi Denki Kabushiki Kaisha Random access memory having separate read out and write in bus lines for reduced access time and operating method therefor

Also Published As

Publication number Publication date
EP0507336B1 (de) 1998-07-08
DE59209399D1 (de) 1998-08-13
EP0507336A2 (de) 1992-10-07
EP0507336A3 (enExample) 1994-01-19
ATE168213T1 (de) 1998-07-15

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Legal Events

Date Code Title Description
8100 Publication of patent without earlier publication of application
D1 Grant (no unexamined application published) patent law 81
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee