DE69210449T2 - Dynamische Speichereinrichtung mit wahlfreiem Zugriff, mit Bitleitungen, die zwischen den Leseverstärkerschaltungen teilweise gemeinsam benutzt werden - Google Patents

Dynamische Speichereinrichtung mit wahlfreiem Zugriff, mit Bitleitungen, die zwischen den Leseverstärkerschaltungen teilweise gemeinsam benutzt werden

Info

Publication number
DE69210449T2
DE69210449T2 DE69210449T DE69210449T DE69210449T2 DE 69210449 T2 DE69210449 T2 DE 69210449T2 DE 69210449 T DE69210449 T DE 69210449T DE 69210449 T DE69210449 T DE 69210449T DE 69210449 T2 DE69210449 T2 DE 69210449T2
Authority
DE
Germany
Prior art keywords
shared
memory device
random access
access memory
bit lines
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69210449T
Other languages
English (en)
Other versions
DE69210449D1 (de
Inventor
Takanori Saeki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Electronics Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Application granted granted Critical
Publication of DE69210449D1 publication Critical patent/DE69210449D1/de
Publication of DE69210449T2 publication Critical patent/DE69210449T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4097—Bit-line organisation, e.g. bit-line layout, folded bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/18—Bit line organisation; Bit line lay-out

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
DE69210449T 1991-02-27 1992-02-24 Dynamische Speichereinrichtung mit wahlfreiem Zugriff, mit Bitleitungen, die zwischen den Leseverstärkerschaltungen teilweise gemeinsam benutzt werden Expired - Fee Related DE69210449T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3032840A JPH04271086A (ja) 1991-02-27 1991-02-27 半導体集積回路

Publications (2)

Publication Number Publication Date
DE69210449D1 DE69210449D1 (de) 1996-06-13
DE69210449T2 true DE69210449T2 (de) 1997-01-02

Family

ID=12370021

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69210449T Expired - Fee Related DE69210449T2 (de) 1991-02-27 1992-02-24 Dynamische Speichereinrichtung mit wahlfreiem Zugriff, mit Bitleitungen, die zwischen den Leseverstärkerschaltungen teilweise gemeinsam benutzt werden

Country Status (5)

Country Link
US (1) US5243558A (de)
EP (1) EP0502398B1 (de)
JP (1) JPH04271086A (de)
KR (1) KR950012024B1 (de)
DE (1) DE69210449T2 (de)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05342855A (ja) * 1992-06-04 1993-12-24 Nec Corp 半導体メモリ回路
US5732010A (en) * 1992-09-22 1998-03-24 Kabushiki Kaisha Toshiba Dynamic random access memory device with the combined open/folded bit-line pair arrangement
JP3302796B2 (ja) * 1992-09-22 2002-07-15 株式会社東芝 半導体記憶装置
US5864181A (en) 1993-09-15 1999-01-26 Micron Technology, Inc. Bi-level digit line architecture for high density DRAMs
US5546349A (en) * 1995-03-13 1996-08-13 Kabushiki Kaisha Toshiba Exchangeable hierarchical data line structure
US5636158A (en) * 1995-03-13 1997-06-03 Kabushiki Kaisha Toshiba Irregular pitch layout for a semiconductor memory device
US6043562A (en) 1996-01-26 2000-03-28 Micron Technology, Inc. Digit line architecture for dynamic memory
JP2002216471A (ja) * 2001-01-17 2002-08-02 Mitsubishi Electric Corp 半導体記憶装置
FR2830365B1 (fr) * 2001-09-28 2004-12-24 St Microelectronics Sa Memoire vive dynamique
US6836427B2 (en) * 2002-06-05 2004-12-28 Micron Technology, Inc. System and method to counteract voltage disturbances in open digitline array dynamic random access memory systems
KR100538883B1 (ko) * 2003-04-29 2005-12-23 주식회사 하이닉스반도체 반도체 메모리 장치
JP4493666B2 (ja) * 2007-01-30 2010-06-30 株式会社ルネサステクノロジ 強誘電体メモリ

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4807194A (en) * 1986-04-24 1989-02-21 Matsushita Electric Industrial Co., Ltd. Seimiconductor memory device having sub bit lines
JPS63104296A (ja) * 1986-10-21 1988-05-09 Nec Corp 半導体記憶装置
JPS63205897A (ja) * 1987-02-20 1988-08-25 Matsushita Electric Ind Co Ltd 半導体記憶装置
JPH07105134B2 (ja) * 1987-08-28 1995-11-13 三菱電機株式会社 半導体記憶装置
JPH02302986A (ja) * 1989-05-16 1990-12-14 Mitsubishi Electric Corp ダイナミック型半導体記憶装置
KR930001737B1 (ko) * 1989-12-29 1993-03-12 삼성전자 주식회사 반도체 메모리 어레이의 워드라인 배열방법
KR920010344B1 (ko) * 1989-12-29 1992-11-27 삼성전자주식회사 반도체 메모리 어레이의 구성방법
US5107459A (en) * 1990-04-20 1992-04-21 International Business Machines Corporation Stacked bit-line architecture for high density cross-point memory cell array

Also Published As

Publication number Publication date
KR950012024B1 (ko) 1995-10-13
EP0502398A1 (de) 1992-09-09
KR920017108A (ko) 1992-09-26
US5243558A (en) 1993-09-07
JPH04271086A (ja) 1992-09-28
EP0502398B1 (de) 1996-05-08
DE69210449D1 (de) 1996-06-13

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: NEC ELECTRONICS CORP., KAWASAKI, KANAGAWA, JP

8339 Ceased/non-payment of the annual fee