DE3887284T2 - Halbleiterspeicherschaltung mit einem verbesserten Rückschreibschema. - Google Patents

Halbleiterspeicherschaltung mit einem verbesserten Rückschreibschema.

Info

Publication number
DE3887284T2
DE3887284T2 DE3887284T DE3887284T DE3887284T2 DE 3887284 T2 DE3887284 T2 DE 3887284T2 DE 3887284 T DE3887284 T DE 3887284T DE 3887284 T DE3887284 T DE 3887284T DE 3887284 T2 DE3887284 T2 DE 3887284T2
Authority
DE
Germany
Prior art keywords
semiconductor memory
memory circuit
improved write
back scheme
scheme
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE3887284T
Other languages
English (en)
Other versions
DE3887284D1 (de
Inventor
Takeo C O Nec Corporatio Fujii
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Publication of DE3887284D1 publication Critical patent/DE3887284D1/de
Application granted granted Critical
Publication of DE3887284T2 publication Critical patent/DE3887284T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4094—Bit-line management or control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4097—Bit-line organisation, e.g. bit-line layout, folded bit lines

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)
DE3887284T 1987-11-17 1988-11-17 Halbleiterspeicherschaltung mit einem verbesserten Rückschreibschema. Expired - Fee Related DE3887284T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62291138A JPH07105137B2 (ja) 1987-11-17 1987-11-17 半導体メモリ

Publications (2)

Publication Number Publication Date
DE3887284D1 DE3887284D1 (de) 1994-03-03
DE3887284T2 true DE3887284T2 (de) 1994-08-04

Family

ID=17764942

Family Applications (1)

Application Number Title Priority Date Filing Date
DE3887284T Expired - Fee Related DE3887284T2 (de) 1987-11-17 1988-11-17 Halbleiterspeicherschaltung mit einem verbesserten Rückschreibschema.

Country Status (4)

Country Link
US (1) US5138578A (de)
EP (1) EP0316902B1 (de)
JP (1) JPH07105137B2 (de)
DE (1) DE3887284T2 (de)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07105140B2 (ja) * 1988-12-16 1995-11-13 日本電気株式会社 半導体メモリ
EP0436073A3 (en) * 1990-01-05 1993-05-26 International Business Machines Corporation Trench-capacitor-one-transistor storage cell and array for dynamic random access memories
JP3101297B2 (ja) * 1990-03-30 2000-10-23 株式会社東芝 半導体メモリ装置
JP3101298B2 (ja) * 1990-03-30 2000-10-23 株式会社東芝 半導体メモリ装置
JP3179793B2 (ja) * 1990-05-30 2001-06-25 三菱電機株式会社 半導体記憶装置およびその読出方法
JP3039793B2 (ja) * 1990-07-05 2000-05-08 株式会社東芝 半導体メモリ装置
JP2685357B2 (ja) * 1990-12-14 1997-12-03 株式会社東芝 半導体記憶装置
JP2715004B2 (ja) * 1991-01-07 1998-02-16 三菱電機株式会社 半導体メモリ装置
KR940001644B1 (ko) * 1991-05-24 1994-02-28 삼성전자 주식회사 메모리 장치의 입출력 라인 프리차아지 방법
US5754478A (en) * 1993-04-20 1998-05-19 Micron Technology, Inc. Fast, low power, write scheme for memory circuits using pulsed off isolation device
JP3919834B2 (ja) * 1994-09-14 2007-05-30 株式会社ルネサステクノロジ 半導体記憶装置
JPH08139290A (ja) * 1994-11-11 1996-05-31 Toshiba Corp 半導体記憶装置
US5673219A (en) * 1996-03-21 1997-09-30 Texas Instruments Incorporated Apparatus and method for reducing leakage current in a dynamic random access memory
US6243308B1 (en) * 2000-02-22 2001-06-05 United Microelectronics Corp. Method for testing dynamic random access memory under wafer-level-burn-in
US6345006B1 (en) * 2000-08-21 2002-02-05 Micron Technology, Inc. Memory circuit with local isolation and pre-charge circuits
JP4229674B2 (ja) * 2002-10-11 2009-02-25 Ｎｅｃエレクトロニクス株式会社 半導体記憶装置及びその制御方法
JP4667888B2 (ja) * 2005-02-01 2011-04-13 パナソニック株式会社 半導体記憶装置
JP2007257786A (ja) * 2006-03-24 2007-10-04 Toshiba Corp 半導体記憶装置
CN117711458B (zh) * 2024-02-06 2024-05-03 浙江力积存储科技有限公司 半导体存储装置及降低其写恢复时间的方法、存储阵列

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6012718B2 (ja) * 1980-03-28 1985-04-03 富士通株式会社 半導体ダイナミックメモリ
US4584672A (en) * 1984-02-22 1986-04-22 Intel Corporation CMOS dynamic random-access memory with active cycle one half power supply potential bit line precharge
US4656613A (en) * 1984-08-29 1987-04-07 Texas Instruments Incorporated Semiconductor dynamic memory device with decoded active loads
KR900005667B1 (ko) * 1984-11-20 1990-08-03 후지쓰 가부시끼가이샤 반도체 기억장치
US4679172A (en) * 1985-05-28 1987-07-07 American Telephone And Telegraph Company, At&T Bell Laboratories Dynamic memory with increased data retention time
JPS62202397A (ja) * 1986-02-28 1987-09-07 Fujitsu Ltd 半導体記憶装置

Also Published As

Publication number Publication date
US5138578A (en) 1992-08-11
EP0316902B1 (de) 1994-01-19
DE3887284D1 (de) 1994-03-03
JPH01130391A (ja) 1989-05-23
EP0316902A2 (de) 1989-05-24
JPH07105137B2 (ja) 1995-11-13
EP0316902A3 (de) 1991-04-24

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee