DE69019697T2 - Reparierbare Speicherschaltung. - Google Patents

Reparierbare Speicherschaltung.

Info

Publication number
DE69019697T2
DE69019697T2 DE69019697T DE69019697T DE69019697T2 DE 69019697 T2 DE69019697 T2 DE 69019697T2 DE 69019697 T DE69019697 T DE 69019697T DE 69019697 T DE69019697 T DE 69019697T DE 69019697 T2 DE69019697 T2 DE 69019697T2
Authority
DE
Germany
Prior art keywords
memory circuit
repairable memory
repairable
circuit
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69019697T
Other languages
English (en)
Other versions
DE69019697D1 (de
Inventor
Andrew Timothy Ferris
Gordon Stirling Work
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics Ltd Great Britain
Original Assignee
Inmos Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Inmos Ltd filed Critical Inmos Ltd
Publication of DE69019697D1 publication Critical patent/DE69019697D1/de
Application granted granted Critical
Publication of DE69019697T2 publication Critical patent/DE69019697T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/84—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved access time or stability
    • G11C29/848—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved access time or stability by adjacent switching
DE69019697T 1989-11-17 1990-10-30 Reparierbare Speicherschaltung. Expired - Fee Related DE69019697T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB898926004A GB8926004D0 (en) 1989-11-17 1989-11-17 Repairable memory circuit

Publications (2)

Publication Number Publication Date
DE69019697D1 DE69019697D1 (de) 1995-06-29
DE69019697T2 true DE69019697T2 (de) 1995-11-16

Family

ID=10666463

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69019697T Expired - Fee Related DE69019697T2 (de) 1989-11-17 1990-10-30 Reparierbare Speicherschaltung.

Country Status (5)

Country Link
US (1) US5163023A (de)
EP (1) EP0434200B1 (de)
JP (1) JP2798497B2 (de)
DE (1) DE69019697T2 (de)
GB (1) GB8926004D0 (de)

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JP2575919B2 (ja) * 1990-03-22 1997-01-29 株式会社東芝 半導体記憶装置の冗長回路
GB9023867D0 (en) * 1990-11-02 1990-12-12 Mv Ltd Improvements relating to a fault tolerant storage system
US5255227A (en) * 1991-02-06 1993-10-19 Hewlett-Packard Company Switched row/column memory redundancy
US5392292A (en) * 1991-06-27 1995-02-21 Cray Research, Inc. Configurable spare memory chips
US5392247A (en) * 1991-09-19 1995-02-21 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device including redundancy circuit
JPH05314788A (ja) * 1992-05-07 1993-11-26 Mitsubishi Electric Corp リダンダンシ回路
US5471479A (en) * 1992-08-06 1995-11-28 Motorola, Inc. Arrangement for column sparing of memory
US5488701A (en) * 1994-11-17 1996-01-30 International Business Machines Corporation In log sparing for log structured arrays
US5694346A (en) * 1995-01-18 1997-12-02 International Business Machines Corporation Integrated circuit including fully testable small scale read only memory constructed of level sensitive scan device shift register latches
US5627786A (en) * 1995-02-10 1997-05-06 Micron Quantum Devices, Inc. Parallel processing redundancy scheme for faster access times and lower die area
US6108237A (en) 1997-07-17 2000-08-22 Micron Technology, Inc. Fast-sensing amplifier for flash memory
US5682496A (en) 1995-02-10 1997-10-28 Micron Quantum Devices, Inc. Filtered serial event controlled command port for memory
US5502676A (en) * 1995-04-24 1996-03-26 Motorola, Inc. Integrated circuit memory with column redundancy having shared read global data lines
US5737344A (en) * 1995-05-25 1998-04-07 International Business Machines Corporation Digital data storage with increased robustness against data loss
US5592102A (en) * 1995-10-19 1997-01-07 Altera Corporation Means and apparatus to minimize the effects of silicon processing defects in programmable logic devices
JP2956634B2 (ja) * 1997-01-27 1999-10-04 日本電気株式会社 半導体記憶装置の冗長アドレス選択方式および半導体記憶装置
US5715198A (en) * 1997-02-03 1998-02-03 International Business Machines Corporation Output latching circuit for static memory devices
US6034536A (en) * 1997-02-05 2000-03-07 Altera Corporation Redundancy circuitry for logic circuits
US6091258A (en) * 1997-02-05 2000-07-18 Altera Corporation Redundancy circuitry for logic circuits
US5764577A (en) * 1997-04-07 1998-06-09 Motorola, Inc. Fusleless memory repair system and method of operation
US6107820A (en) * 1997-05-23 2000-08-22 Altera Corporation Redundancy circuitry for programmable logic devices with interleaved input circuits
JP3157753B2 (ja) * 1997-09-30 2001-04-16 日本電気アイシーマイコンシステム株式会社 半導体記憶回路
KR100252053B1 (ko) * 1997-12-04 2000-05-01 윤종용 칼럼 방향의 데이터 입출력선을 가지는 반도체메모리장치와불량셀 구제회로 및 방법
JP4519208B2 (ja) * 1998-03-03 2010-08-04 株式会社東芝 半導体記憶装置
JP3206541B2 (ja) * 1998-03-04 2001-09-10 日本電気株式会社 半導体記憶装置
US6201404B1 (en) 1998-07-14 2001-03-13 Altera Corporation Programmable logic device with redundant circuitry
US6163489A (en) * 1999-07-16 2000-12-19 Micron Technology Inc. Semiconductor memory having multiple redundant columns with offset segmentation boundaries
KR100354437B1 (ko) * 2000-01-28 2002-09-28 삼성전자 주식회사 내장 메모리를 위한 자기 복구 회로를 구비하는 집적회로반도체 장치 및 메모리 복구 방법
JP4191355B2 (ja) * 2000-02-10 2008-12-03 株式会社ルネサステクノロジ 半導体集積回路装置
JP3822412B2 (ja) 2000-03-28 2006-09-20 株式会社東芝 半導体記憶装置
US7230600B1 (en) * 2000-09-28 2007-06-12 Intel Corporation Repairable memory in display devices
US6535436B2 (en) 2001-02-21 2003-03-18 Stmicroelectronics, Inc. Redundant circuit and method for replacing defective memory cells in a memory device
KR100403480B1 (ko) * 2001-08-23 2003-10-30 플래시스 주식회사 반도체 메모리 장치 및 이를 이용한 읽기/쓰기 동작 방법
US7000155B2 (en) * 2003-04-21 2006-02-14 International Business Machines Corporation Redundancy register architecture for soft-error tolerance and methods of making the same
US8041989B2 (en) * 2007-06-28 2011-10-18 International Business Machines Corporation System and method for providing a high fault tolerant memory system
US8041990B2 (en) * 2007-06-28 2011-10-18 International Business Machines Corporation System and method for error correction and detection in a memory system
US7974805B2 (en) * 2008-10-14 2011-07-05 ON Semiconductor Trading, Ltd Image sensor and method
US7881134B2 (en) * 2008-11-17 2011-02-01 Micron Technology, Inc. Replacing defective columns of memory cells in response to external addresses
US8898511B2 (en) 2010-06-24 2014-11-25 International Business Machines Corporation Homogeneous recovery in a redundant memory system
US8631271B2 (en) 2010-06-24 2014-01-14 International Business Machines Corporation Heterogeneous recovery in a redundant memory system
US8549378B2 (en) 2010-06-24 2013-10-01 International Business Machines Corporation RAIM system using decoding of virtual ECC
US8484529B2 (en) 2010-06-24 2013-07-09 International Business Machines Corporation Error correction and detection in a redundant memory system
US8522122B2 (en) 2011-01-29 2013-08-27 International Business Machines Corporation Correcting memory device and memory channel failures in the presence of known memory device failures
KR20190012566A (ko) * 2017-07-27 2019-02-11 삼성전자주식회사 에러 정정 기능을 갖는 메모리 시스템, 메모리 모듈 및 메모리 컨트롤러의 동작 방법
US10592367B2 (en) * 2017-09-15 2020-03-17 Apple Inc. Redundancy implementation using bytewise shifting
US10658067B2 (en) * 2018-05-14 2020-05-19 Micron Technology, Inc. Managing data disturbance in a memory with asymmetric disturbance effects
US11581035B2 (en) * 2021-02-24 2023-02-14 Micron Technology, Inc. Systems, devices, and methods for efficient usage of IO section breaks in memory devices
US11514977B2 (en) * 2021-04-01 2022-11-29 Micron Technology, Inc. Memory devices implementing data-access schemes for digit lines proximate to edges of column planes, and related devices, systems, and methods
CN116072195B (zh) * 2023-04-06 2023-08-18 长鑫存储技术有限公司 存储器

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4346459A (en) * 1980-06-30 1982-08-24 Inmos Corporation Redundancy scheme for an MOS memory
US4389715A (en) * 1980-10-06 1983-06-21 Inmos Corporation Redundancy scheme for a dynamic RAM
US4459685A (en) * 1982-03-03 1984-07-10 Inmos Corporation Redundancy system for high speed, wide-word semiconductor memories
JPS59144098A (ja) * 1983-02-08 1984-08-17 Fujitsu Ltd 半導体記憶装置
GB2154032B (en) * 1984-02-08 1988-04-20 Inmos Ltd A repairable memory array
FR2611301B1 (fr) * 1987-02-24 1989-04-21 Thomson Semiconducteurs Memoire integree avec redondance de colonnes de donnees
JP2590897B2 (ja) * 1987-07-20 1997-03-12 日本電気株式会社 半導体メモリ
JPH0289299A (ja) * 1988-09-27 1990-03-29 Nec Corp 半導体記憶装置

Also Published As

Publication number Publication date
DE69019697D1 (de) 1995-06-29
EP0434200A1 (de) 1991-06-26
JPH03176899A (ja) 1991-07-31
GB8926004D0 (en) 1990-01-10
JP2798497B2 (ja) 1998-09-17
US5163023A (en) 1992-11-10
EP0434200B1 (de) 1995-05-24

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: SGS-THOMSON MICROELECTRONICS LTD., MARLOW, BUCKING

8339 Ceased/non-payment of the annual fee