DE3788438D1 - Methode zur Herstellung von integrierten elektronischen Vorrichtungen, insbesondere Hochspannungs-P-Kanal-MOS-Transistoren. - Google Patents

Methode zur Herstellung von integrierten elektronischen Vorrichtungen, insbesondere Hochspannungs-P-Kanal-MOS-Transistoren.

Info

Publication number
DE3788438D1
DE3788438D1 DE87100765T DE3788438T DE3788438D1 DE 3788438 D1 DE3788438 D1 DE 3788438D1 DE 87100765 T DE87100765 T DE 87100765T DE 3788438 T DE3788438 T DE 3788438T DE 3788438 D1 DE3788438 D1 DE 3788438D1
Authority
DE
Germany
Prior art keywords
voltage
electronic devices
channel mos
mos transistors
especially high
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE87100765T
Other languages
English (en)
Other versions
DE3788438T2 (de
Inventor
Claudio Contiero
Paola Galbiati
Antonio Andreini
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SRL
Original Assignee
SGS Thomson Microelectronics SRL
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SGS Thomson Microelectronics SRL filed Critical SGS Thomson Microelectronics SRL
Publication of DE3788438D1 publication Critical patent/DE3788438D1/de
Application granted granted Critical
Publication of DE3788438T2 publication Critical patent/DE3788438T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H01L21/2652—Through-implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2252—Diffusion into or out of group IV semiconductors using predeposition of impurities into the semiconductor surface, e.g. from a gaseous phase
    • H01L21/2253—Diffusion into or out of group IV semiconductors using predeposition of impurities into the semiconductor surface, e.g. from a gaseous phase by ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8236—Combination of enhancement and depletion transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8248—Combination of bipolar and field-effect technology
    • H01L21/8249—Bipolar and MOS technology

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Bipolar Integrated Circuits (AREA)
  • Bipolar Transistors (AREA)
DE87100765T 1986-01-24 1987-01-21 Methode zur Herstellung von integrierten elektronischen Vorrichtungen, insbesondere Hochspannungs-P-Kanal-MOS-Transistoren. Expired - Fee Related DE3788438T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT19173/86A IT1188309B (it) 1986-01-24 1986-01-24 Procedimento per la fabbricazione di dispositivi elettronici integrati,in particolare transistori mos a canale p ad alta tensione

Publications (2)

Publication Number Publication Date
DE3788438D1 true DE3788438D1 (de) 1994-01-27
DE3788438T2 DE3788438T2 (de) 1994-04-07

Family

ID=11155505

Family Applications (1)

Application Number Title Priority Date Filing Date
DE87100765T Expired - Fee Related DE3788438T2 (de) 1986-01-24 1987-01-21 Methode zur Herstellung von integrierten elektronischen Vorrichtungen, insbesondere Hochspannungs-P-Kanal-MOS-Transistoren.

Country Status (5)

Country Link
US (1) US4721686A (de)
EP (1) EP0231811B1 (de)
JP (1) JP2721877B2 (de)
DE (1) DE3788438T2 (de)
IT (1) IT1188309B (de)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1213411B (it) * 1986-12-17 1989-12-20 Sgs Microelettronica Spa Struttura mos di potenza con dispositivo di protezione contro le sovratensioni e processo per lasua fabbricazione.
US4931407A (en) * 1987-06-25 1990-06-05 Kabushiki Kaisha Toshiba Method for manufacturing integrated bipolar and MOS transistors
KR930008899B1 (ko) * 1987-12-31 1993-09-16 금성일렉트론 주식회사 트랜칭(trenching)에 의한 바이-씨모스(Bi-CMOS)제조방법
JP2623635B2 (ja) * 1988-02-16 1997-06-25 ソニー株式会社 バイポーラトランジスタ及びその製造方法
US4943536A (en) * 1988-05-31 1990-07-24 Texas Instruments, Incorporated Transistor isolation
NL8802219A (nl) * 1988-09-09 1990-04-02 Philips Nv Werkwijze voor het vervaardigen van een halfgeleiderinrichting met een siliciumlichaam waarin door ionenimplantaties halfgeleidergebieden worden gevormd.
JPH06101540B2 (ja) * 1989-05-19 1994-12-12 三洋電機株式会社 半導体集積回路の製造方法
US5254486A (en) * 1992-02-21 1993-10-19 Micrel, Incorporated Method for forming PNP and NPN bipolar transistors in the same substrate
JPH06342914A (ja) * 1993-06-01 1994-12-13 Nec Corp 半導体装置の製造方法
EP0676802B1 (de) * 1994-03-31 1998-12-23 STMicroelectronics S.r.l. Verfahren zur Herstellung eines Halbleiterbauteils mit vergrabenem Übergang
JPH08172139A (ja) * 1994-12-19 1996-07-02 Sony Corp 半導体装置製造方法
EP0818055A4 (de) * 1995-03-27 1998-05-06 Micrel Inc Selbstausrichtende technik für halbleiteranordnungen
US6017785A (en) * 1996-08-15 2000-01-25 Integrated Device Technology, Inc. Method for improving latch-up immunity and interwell isolation in a semiconductor device
JP3527148B2 (ja) * 1999-09-24 2004-05-17 日本電気株式会社 半導体装置の製造方法
US6451645B1 (en) 2000-07-12 2002-09-17 Denso Corp Method for manufacturing semiconductor device with power semiconductor element and diode
US20060148188A1 (en) * 2005-01-05 2006-07-06 Bcd Semiconductor Manufacturing Limited Fabrication method for bipolar integrated circuits

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL162511C (nl) * 1969-01-11 1980-05-16 Philips Nv Geintegreerde halfgeleiderschakeling met een laterale transistor en werkwijze voor het vervaardigen van de geintegreerde halfgeleiderschakeling.
US3915767A (en) * 1973-02-05 1975-10-28 Honeywell Inc Rapidly responsive transistor with narrowed base
US4087900A (en) * 1976-10-18 1978-05-09 Bell Telephone Laboratories, Incorporated Fabrication of semiconductor integrated circuit structure including injection logic configuration compatible with complementary bipolar transistors utilizing simultaneous formation of device regions
JPS543479A (en) * 1977-06-09 1979-01-11 Toshiba Corp Semiconductor device and its manufacture
US4485552A (en) * 1980-01-18 1984-12-04 International Business Machines Corporation Complementary transistor structure and method for manufacture
NL8006827A (nl) * 1980-12-17 1982-07-16 Philips Nv Werkwijze voor het vervaardigen van een halfgeleiderinrichting.
NL8103218A (nl) * 1981-07-06 1983-02-01 Philips Nv Veldeffekttransistor met geisoleerde stuurelektrode.
US4435895A (en) * 1982-04-05 1984-03-13 Bell Telephone Laboratories, Incorporated Process for forming complementary integrated circuit devices
US4507847A (en) * 1982-06-22 1985-04-02 Ncr Corporation Method of making CMOS by twin-tub process integrated with a vertical bipolar transistor
JPS60234357A (ja) * 1984-05-08 1985-11-21 Toshiba Corp 半導体装置の製造方法

Also Published As

Publication number Publication date
US4721686A (en) 1988-01-26
JP2721877B2 (ja) 1998-03-04
JPS62183553A (ja) 1987-08-11
IT1188309B (it) 1988-01-07
EP0231811A2 (de) 1987-08-12
DE3788438T2 (de) 1994-04-07
EP0231811B1 (de) 1993-12-15
EP0231811A3 (en) 1988-03-02
IT8619173A0 (it) 1986-01-24

Similar Documents

Publication Publication Date Title
DE3788438D1 (de) Methode zur Herstellung von integrierten elektronischen Vorrichtungen, insbesondere Hochspannungs-P-Kanal-MOS-Transistoren.
DE3782367D1 (de) Mos-halbleiterschaltung.
DE3881304D1 (de) Mos-transistor.
DE3381215D1 (de) Integrierte halbleiterschaltungen und verfahren zur herstellung.
DE3650323D1 (de) VLSI-Chip und Verfahren zur Herstellung.
DE3777497D1 (de) Herstellungsverfahren fuer gestapelte mos-bauelemente.
DE3685124D1 (de) Integriertes halbleiterschaltungsbauelement und verfahren zu seiner herstellung.
DE3682021D1 (de) Polysilizium-mos-transistor und verfahren zu seiner herstellung.
DE3681934D1 (de) Integrierter mos-transistor und verfahren zu seiner herstellung.
DE3769174D1 (de) Indolizin-derivate, verfahren zur herstellung und diese enthaltende zusammensetzungen.
DE3873839D1 (de) Mos-leistungstransistoranordnung.
DE3788527D1 (de) Bipolarer Transistor und sein Herstellungsverfahren.
DE3789826D1 (de) MOS-Halbleiteranordnung und Herstellungsverfahren.
DE3783918D1 (de) Verfahren zur herstellung von iodierten aromatischen verbindungen.
DE3866016D1 (de) Mos-transistor-brueckenschaltung.
DE3584644D1 (de) Verfahren zur herstellung einer halbleiteranordnung mit p-kanal und n-kanal misfets.
DE3768854D1 (de) Lateraltransistor.
DE3378446D1 (en) Integrated semiconductor circuit, comprising bipolar and mos transistors on the same chip, and method of making the same
DE3779786D1 (de) Logisches mos-dominogatter.
DE69015494D1 (de) Selbstausrichtende Justiermarke für die Herstellung von integrierten Schaltungen.
DE3786785D1 (de) Verfahren zur herstellung von mos-bauelementen fuer integrierte schaltungen.
DE3789350D1 (de) Herstellungsverfahren zur Ausbildung eines MOS-Transistors durch Selbstausrichtung der Source/Drain-Gebiete.
DE69014707D1 (de) Verfahren zur Herstellung von CMOS-Feldeffekt-Transistoren.
DE3673777D1 (de) Ein monolithisch integrierter schaltkreis, insbesondere vom mos oder cmos-typ und verfahren zu seiner herstellung.
DE3788120D1 (de) Verfahren zur herstellung gestapelter mos-strukturen.

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: STMICROELECTRONICS S.R.L., AGRATE BRIANZA, MAILAND

8339 Ceased/non-payment of the annual fee