EP0818055A4 - Selbstausrichtende technik für halbleiteranordnungen - Google Patents

Selbstausrichtende technik für halbleiteranordnungen

Info

Publication number
EP0818055A4
EP0818055A4 EP96906603A EP96906603A EP0818055A4 EP 0818055 A4 EP0818055 A4 EP 0818055A4 EP 96906603 A EP96906603 A EP 96906603A EP 96906603 A EP96906603 A EP 96906603A EP 0818055 A4 EP0818055 A4 EP 0818055A4
Authority
EP
European Patent Office
Prior art keywords
self
semiconductor devices
alignment technique
alignment
technique
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP96906603A
Other languages
English (en)
French (fr)
Other versions
EP0818055A1 (de
Inventor
Martin E Garnett
James C Moyer
Martin J Alter
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Microchip Technology Inc
Original Assignee
Micrel Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micrel Inc filed Critical Micrel Inc
Publication of EP0818055A1 publication Critical patent/EP0818055A1/de
Publication of EP0818055A4 publication Critical patent/EP0818055A4/de
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8248—Combination of bipolar and field-effect technology
    • H01L21/8249—Bipolar and MOS technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/761—PN junctions

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Bipolar Transistors (AREA)
EP96906603A 1995-03-27 1996-02-21 Selbstausrichtende technik für halbleiteranordnungen Withdrawn EP0818055A4 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US41136895A 1995-03-27 1995-03-27
US411368 1995-03-27
PCT/US1996/002449 WO1996030936A1 (en) 1995-03-27 1996-02-21 Self-alignment technique for semiconductor devices

Publications (2)

Publication Number Publication Date
EP0818055A1 EP0818055A1 (de) 1998-01-14
EP0818055A4 true EP0818055A4 (de) 1998-05-06

Family

ID=23628653

Family Applications (1)

Application Number Title Priority Date Filing Date
EP96906603A Withdrawn EP0818055A4 (de) 1995-03-27 1996-02-21 Selbstausrichtende technik für halbleiteranordnungen

Country Status (4)

Country Link
EP (1) EP0818055A4 (de)
JP (1) JP3092854B2 (de)
AU (1) AU4993896A (de)
WO (1) WO1996030936A1 (de)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6861711B2 (en) 2003-01-03 2005-03-01 Micrel, Incorporated Thick gate oxide transistor and electrostatic discharge protection utilizing thick gate oxide transistors
US6864537B1 (en) 2003-01-03 2005-03-08 Micrel, Incorporated Thick gate oxide transistor and electrostatic discharge protection utilizing thick gate oxide transistors
US6888710B2 (en) 2003-01-03 2005-05-03 Micrel, Incorporated Insulated gate bipolar transistor and electrostatic discharge cell protection utilizing insulated gate bipolar transistors

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4021270A (en) * 1976-06-28 1977-05-03 Motorola, Inc. Double master mask process for integrated circuit manufacture
WO1995002898A1 (en) * 1993-07-12 1995-01-26 National Semiconductor Corporation Process for fabricating semiconductor devices having arsenic emitters

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1188309B (it) * 1986-01-24 1988-01-07 Sgs Microelettrica Spa Procedimento per la fabbricazione di dispositivi elettronici integrati,in particolare transistori mos a canale p ad alta tensione
US5141881A (en) * 1989-04-20 1992-08-25 Sanyo Electric Co., Ltd. Method for manufacturing a semiconductor integrated circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4021270A (en) * 1976-06-28 1977-05-03 Motorola, Inc. Double master mask process for integrated circuit manufacture
WO1995002898A1 (en) * 1993-07-12 1995-01-26 National Semiconductor Corporation Process for fabricating semiconductor devices having arsenic emitters

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of WO9630936A1 *

Also Published As

Publication number Publication date
EP0818055A1 (de) 1998-01-14
JPH10508433A (ja) 1998-08-18
AU4993896A (en) 1996-10-16
JP3092854B2 (ja) 2000-09-25
WO1996030936A1 (en) 1996-10-03

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Legal Events

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