WO1995002898A1 - Process for fabricating semiconductor devices having arsenic emitters - Google Patents

Process for fabricating semiconductor devices having arsenic emitters Download PDF

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Publication number
WO1995002898A1
WO1995002898A1 PCT/US1994/007682 US9407682W WO9502898A1 WO 1995002898 A1 WO1995002898 A1 WO 1995002898A1 US 9407682 W US9407682 W US 9407682W WO 9502898 A1 WO9502898 A1 WO 9502898A1
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Prior art keywords
region
epitaxial layer
defining
windows
masking
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PCT/US1994/007682
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French (fr)
Inventor
Mark Redford
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National Semiconductor Corporation
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Filing date
Publication date
Application filed by National Semiconductor Corporation filed Critical National Semiconductor Corporation
Priority to KR1019960700076A priority Critical patent/KR960704351A/en
Priority to EP94923385A priority patent/EP0710399A1/en
Priority to JP7504626A priority patent/JPH09500760A/en
Publication of WO1995002898A1 publication Critical patent/WO1995002898A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H01L21/2652—Through-implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/761—PN junctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/66166—Resistors with PN junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/66181—Conductor-insulator-semiconductor capacitors, e.g. trench capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/6625—Lateral transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66257—Schottky transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66272—Silicon vertical transistors

Definitions

  • the present invention relates to a process for fabricating semiconductor devices, and more particularly but not by way of limitation, to a process for fabricating semiconductor devices having arsenic emitters.
  • An NPN transistor is a fundamental circuit element of bipolar integrated circuits. Structurally, a bipolar NPN transistor has an N type collector and an N type emitter separated by a P type base.
  • the collector is an island of N type material located on top of a P type substrate; the base region is an island of P type material located within the collector region; and the emitter is an island of N type material located within the base. Electrical contacts are provided to the collector, the emitter and the base.
  • a low resistivity layer is located under the base and collector contacts so as to minimize the internal resistance of the collector.
  • the collector region which is an N type
  • epitaxial layer formed on the top of the P type substrate is isolated from adjacent devices by a P type isolation region or a region of silicon dioxide.
  • circuit density An important consideration in the fabrication of semiconductor devices is circuit density. Higher circuit density allows more devices to be fabricated on a single wafer, thereby lowering the cost of individual circuits. Factors adversely affecting circuit density are lateral diffusion of doped regions and mask alignment.
  • NPN transistors having phosphorus emitters have heretofore been employed in an effort to provide semiconductor devices having improved circuit density.
  • one major concern in the fabrication of NPN transistors having phosphorus emitters is the beta variations which occur across the wafer. These beta variations are believed to be due to the temperature variation which occur across the wafer during the fabrication process. That is, at low diffusion temperatures the diffusion coefficients for phosphorus vary, thereby resulting in varying emitter-base pinch resistances and consequently varying beta values.
  • a process for fabricating a bipolar transistor in a wafer.
  • the wafer is a semiconductor structure that includes a silicon substrate of a first conductivity type, an epitaxial layer of a second conductivity type and a buried layer of the second conductivity type disposed between a portion of the substrate and the epitaxial layer.
  • the process includes the steps of:
  • (11) forming electrical connections to the emitter region, the base region, the collector region and the isolation region through the window defining the emitter region and the windows for providing the ohmic connections to the base region, the collector contact region and the isolation region of the epitaxial layer.
  • bipolar transistors produced employing arsenic ions and boron ions as conductive type impurities do not suffer from beta variation across the wafer and yet yield substantially the same base, emitter and emitter-base pinch resistances as bipolar transistors employing phosphorus ions as one of the conductive type impurities. That is, the bipolar transistors produced in accordance with the process of the present invention wherein arsenic and boron ions are employed as conductive impurities possess similar electrical characteristics as bipolar
  • bipolar transistors produced using phosphorus process technology but the bipolar transistors produced in accordance with the process of the present invention do not suffer from the beta variations across the wafers as do bipolar transistors produced using phosphorus process technology.
  • an object of the present invention is to provide a bipolar transistor in a wafer which possesses
  • Another object of the present invention while achieving the above-stated object, is to provide an improved process for fabricating a bipolar transistor in a wafer having a silicon substrate of a first conductivity type, an epitaxial layer of a second conductivity type and a buried layer of the second conductivity type disposed between a portion of the substrate and the epitaxial layer.
  • FIG. 1 is a diagrammatical cross-sectional view of a wafer after formation of a buried layer in a process for fabricating an NPN transistor according to the present invention.
  • FIG. 2 is a diagrammatical cross-sectional view of the wafer after formation of openings in a first oxide layer to define a collector contact region, a base region and an emitter region.
  • FIG. 3 is a diagrammatical cross-sectional view of the wafer after implantation of the collector contact region.
  • FIG. 4 is a diagrammatical cross-sectional view of the wafer after implantation of the isolation region.
  • FIG. 5 is a diagrammatical cross-sectional view of the wafer after implantation of the base region.
  • FIG. 6 is a diagrammatical cross-sectional view of the wafer after deposition of a second oxide layer and formation of openings in the second oxide layer to define an emitter region and ohmic contact region.
  • FIG. 7 is a diagrammatical cross-sectional view of the wafer after implantation of the emitter region.
  • FIG. 8 is a diagrammatical cross-sectional view of the wafer after deposition and patterning of a metallization layer.
  • FIG. 9 is a diagrammatical cross-sectional view of a Schottky transistor fabricated in accordance with the process of the present invention.
  • FIG. 10 is a diagrammatical cross-sectional view of a capacitor fabricated in accordance with the process of the present invention.
  • FIG. 11 is a diagrammatical cross-sectional view of an implant resistor fabricated in accordance with the process of the present invention.
  • FIG. 12 is a diagrammatical cross-sectional view of a lateral PNP transistor fabricated in accordance with the process of the present invention.
  • the present invention relates to a process for fabricat- ing integrated circuits having bipolar transistors and other circuit elements.
  • the process for fabricating NPN bipolar transistors is described in detail hereinafter with reference to FIGS. 1-8.
  • the silicon substrate 12 has a crystallographic orientation of ⁇ 111>, as designated by Miller indices, and a resistivity in the range of 1.5 to 3.0 ohm-centimeters.
  • the surface of the silicon substrate 12 is desirably positioned 4.5 degrees off the ⁇ 111> direction toward the nearest ⁇ 110> direction. Such substrates are commonly used for the fabrication of bipolar devices.
  • substrate refers to the P type region of silicon upon and partially within which the integrated circuits are fabricated; and the term “wafer” includes the substrate and the features and elements fabricated on top of the substrate.
  • the wafer 14 is first thermally oxidized to form a layer of silicon dioxide (oxide) 16 on a upper surface of the silicon substrate 12.
  • oxide silicon dioxide
  • An oxide thickness of approximately 8000 Angstroms is preferred.
  • a first masking layer (not shown) is deposited over a portion of the substrate 12 so that a window 18 is opened in the silicon dioxide layer 16 to enable formation of a buried layer. This is desirably done
  • the substrate 12 has a portion exposed through the window 18 in the silicon dioxide layer 16.
  • N type impurity preferably antimony
  • the silicon dioxide layer 16 is removed by etching in hydrofluoric acid.
  • dichlorosilane is then applied to the substrate 12 so as to form an epitaxial layer 22 on the top of the buried layer 20 and the substrate 12.
  • the epitaxial layer 22 is lightly doped N conductivity and has the same crystallographic orientation as the substrate 12.
  • the thickness and resistivity of the epitaxial layer 22 will affect the operational characteristics of the transistor, e.g. gain and breakdown voltage.
  • the thickness of the epitaxial layer 22 is desirably between 2.5 and 3.1 microns and the resistivity is between 0.7 and 1.1 ohm-centimeters, with the optimum values in the center of each range.
  • the resistance falls outside the range, either the breakdown voltage or the gain of the transistor will decrease to unacceptable levels.
  • suitable results have been obtained wherein chemical vapor techniques are employed using arsine as a dopant.
  • the concentration of the arsine i.e. the dopant controls the resistivity of the resulting epitaxial layer 22.
  • the top surface of the epitaxial layer 22 is then oxidized to form a layer of silicon dioxide 24.
  • the silicon oxide layer 24 is grown by placing the wafer 14 in an oxidizing atmosphere at an elevated temperature.
  • the epitaxial layer 22 is oxidized until the silicon dioxide layer 24 is provided with a nominal thickness of approximately 1000 Angstroms.
  • a layer of silicon nitride 26 can be deposited on top of the silicon dioxide layer 24 by use of low pressure chemical deposition.
  • Windows 28, 30 and 32 are defined in the silicon dioxide and silicon nitride layers 24, 26, respectively, by a first masking layer 33 formed over selected portions of the silicon nitride layer 26 by application of a first mask.
  • Formation of the windows 28, 30 and 32 exposes the upper surface of the epitaxial layer 22 to define a collector contact region 34, a base region 36 and an isolation region 38.
  • the isolation region 38 encircles the collector contact region 34, the base region 36 and the buried layer 20.
  • the exposed areas of the epitaxial layer 22 are oxidized (see FIG. 3).
  • the oxidation of the exposed areas of the epitaxial layer 22 is achieved by thermally growing a layer of silicon dioxide 40 to a nominal thickness of about 1000 Angstroms.
  • subsequent ion implantation of the collector contact region 34 and isolation region 38 can be performed through the silicon dioxide layer 40 and the problem of ion channeling is substantially alleviated.
  • a second masking layer 42 is deposited over the base region 36 and the isolation region 38 by application of a second mask.
  • the upper surface of the wafer 14 is coated with a layer of photoresist material; and the photoresist material is then developed by exposing the photoresist material through a mask. After developing, the second masking layer 42 covers the base and isolation regions 34 and 36, while the collector contact region 32 remains exposed.
  • the second masking layer 42 is oversized with respect to the base and isolation regions 36, 38. Thus, the alignment of the second masking layer 42 with respect to the wafer 14 is not
  • the alignment of the second masking layer 42 is sufficiently precise to insure that the collector contact region 34 is exposed while the base region 36 and the isolation region 38 are covered.
  • the collector contact region 34 is then implanted to form a heavy doped N+ region 44.
  • Phosphorus atoms are implanted through the silicon oxide layer 40 at an implantation energy of about 80 KeV and at a dosage sufficient to provide about 1 e+15 atoms of arsenic per square centimeter.
  • the wafer 14, at this step in the process, is illustrated in FIG. 3.
  • the resulting heavily doped N+ region 44 does not extend all the way down to the N+ buried layer 20.
  • the isolation region 38 is thereafter doped and the collector contact region 34 and the base region 36 are masked using the following procedures.
  • the second masking layer 42 is removed; and a third masking layer 46 of photoresist material is formed over the collector contact and base regions 34, 36 as illustrated in FIG. 4. A portion of the third masking layer 46 is partially removed to expose the isolation region 38.
  • the alignment of the third masking layer 46 is not critical because the third masking layer 46 is oversized.
  • the isolation region 38 is then ion implanted through the silicon dioxide layer 40 with aluminum ions to form a heavily doped P+ region 48. While the implantation energy and dosage of the aluminum ions are not critical, desirable results can be obtained when the implantation energy employed to implant the aluminum ions is about 120 KeV and the dosage of the aluminum ions is sufficient to provide about 5 e-H4 atoms of aluminum per square centimeter.
  • the collector contact region 34 and the isolation region 38 are annealed so that diffusion of the aluminum ions occurs. Such is accomplished by removing the third masking layer 46 and thereafter heating the wafer 14 to an elevated temperature of about 1000 degrees Celsius in a nitrogen atmosphere for a period of from about 175 to about 195 minutes in a diffusion furnace. At the elevated temperature, annealing occurs to repair crystal lattice damage caused by ion implantation. Diffusion of the dopant ions also occurs, causing the doped regions to expand. The collector contact region 34, the isolation region 38 and the buried N+ region 20 all expand in size. However, at this point, the P-f doped isolation region 38 has not yet joined with the P substrate 12 to complete the electrical isolation of the transistor. A subsequent diffusion step is employed to join the P+ doped isolation region 38 and the P substrate 12.
  • One important aspect of the present invention is the use of aluminum doped isolation.
  • Well known oxide isolation is not practical because of the relatively thick epitaxial layer used in linear transistors.
  • Boron doped isolation results in excessive lateral diffusion because of the combination of the slow diffusivity of boron and the thickness of the epitaxial layer through which the dopant must diffuse.
  • Two advantages of using aluminum as a dopant are: (1) the total time in the diffusion furnace is reduced as compared to boron doped isolation and, as a result, upward diffusion of the buried layer is reduced, enabling use of a much thinner epitaxial layer; and (2) lateral diffusion is reduced thereby permitting circuit elements to be more closely spaced, thus increasing circuit density.
  • the thicker silicon dioxide layer 50 better protects the surface of the epitaxial layer 22 during a subsequent etching step. It is desirable that the thicker silicon dioxide layer 50 be thermally formed to a nominal thickness of about 1000 Angstroms. Alternatively, another option is to oxidize the silicon dioxide layer 40 to form an additional 350 Angstroms to the existing 650 Angstroms of the silicon dioxide layer 40. Of course, one may continue with only the initial silicon dioxide layer 40, but at the added risk of damaging the emitter region during subsequent dry etching.
  • the next steps of the process involve doping the base region 36 while masking the collector contact region 34.
  • a fourth masking layer 52 of photoresist is formed (using a fourth mask) which covers the collector contact region 34, while maintaining the base region 36 and the isolation region 38 in an exposed
  • Boron ions are then implanted through the thicker silicon dioxide layer 50 and into the base region 36 and the isolation region 38 at an implant energy of about 35 Kev and at a dosage of about 3.1 e+14 atoms of boron per square centimeter so as to create a heavily doped P+ region 54, while increase the buried P+ region 48 by doping of the isolation region 38.
  • the base region 36 is fully doped by this implantation step so that a subsequent implantation is not required.
  • the isolation region 38 may be masked to prevent implantation of boron ions into the isolation region 38.
  • the implanted base region 36 and the implanted isolation region 38 are then annealed and diffused in a nitrogen atmosphere by placing the wafer 14 in a furnace maintained at a temperature of about 1000 degrees Celsius for a period of from about 175 to about 195 minutes. At this elevated temperature, all the doped regions increase in size.
  • the crystal lattice in the base and isolation regions 36, 38 are annealed to repair implantation damage. As illustrated in FIG. 5, this diffusion step causes the P+ region 48 to diffuse downward so that the isolation region 38 and the P substrate 12 are united, thereby isolating the portion of the epitaxial layer 22 in which the transistor is formed.
  • the layer of silicon nitride 26 is then removed to expose the silicon dioxide layer 50. This may be accomplished by etching using hot phosphoric acid. As an
  • a small amount of arsenic can be any small amount of arsenic.
  • a layer of silicon dioxide 56 is deposited on top of silicon dioxide layer 50.
  • Any oxide deposition process that is performed at a temperature of about 750 degrees Celsius or less may be used.
  • desirable results can be obtained when a low temperature oxide (LTO) process is used at a temperature of about 420 degrees Celsius to deposit about 4000 Angstroms of silicon dioxide.
  • LTO low temperature oxide
  • the low temperature of the process prevents the formation of defects in the base region 36 which would occur at a higher temperature.
  • a fifth masking layer (not shown) is deposited over the silicon dioxide layer 56 by application of a fifth mask so that windows 58, 60, 62 and 64 are defined in silicon dioxide layers 50 and 56.
  • the windows 58, 60 and 62 expose areas of the isolation region 38, the collector contact region 34 and the base region 36 to be used as ohmic
  • the window 64 exposes an area of the base region 36 defining an emitter region 66 (see FIG. 7) in which an emitter will be formed.
  • the portions of the silicon dioxide layers 50, 56 which are within the confines of the windows 58, 60, 62 and 64 are then etched away, leaving the wafer 14 as shown in FIG. 6.
  • the emitter region 66 is doped while masking the base region 36 and the isolation region 38.
  • a sixth masking layer 68 of photoresist is formed using a sixth mask covering the isolation region 38 and the base region 36, with the collector contact region 34 and the emitter region 66 exposed.
  • Arsenic ions are then implanted into the emitter region 66 and the collector contact region 34 at an implant energy of about 50 KeV and at a dosage of about 7.5 e+15 atoms of arsenic per square centimeters so as to create a heavily doped N+ region and to add to the doping of the collector contact region 34.
  • the collector contact region 34 may be covered by the sixth masking layer 68 to prevent further implantation.
  • the sixth masking layer 68 is stripped, and the implanted regions annealed by heating the wafer 14 to a temperature of about 1000 degrees Celsius for a period of time of from about 240 to about 270 minutes in a nitrogen atmosphere.
  • the wafer 14 illustrated in FIG. 8 includes metal contact 70, 72, 74 and 76, which are respectively connected to the silicon substrate 12, the collector contact region 34, the base region 36, and the emitter region 66.
  • a layer of silicon dioxide is deposited over the first metal layer so as to insulate the second metal layer from the first metal layer. Windows are then opened in the silicon oxide layer and the second metal layer deposited. The metal is patterned by another masking process, and then alloyed. A passivation oxide is deposited on top of the wafer 14 and then windows are opened to external contact pads. The wafer 14 is now ready for dicing.
  • NPN LVceo 15.5 15.4 it should be noted that the beta increases by approximately 15% as a consequence of the arsenic emitter. This could be easily fine tuned at the emitter diffusion process. However, the LVceo of the two emitters is substantially the same. Analysis of the above data indicates that the difference in the NPN Beta parameter of the two emitters is due to avalanche (emitter acceleration) which is driven to some degree by beta.
  • Example 1 In order to further illustrate the process of the present invention for fabricating a bipolar transistor having an arsenic emitter the following example is given. However, it is to be understood that the example is for illustrative purposes only and is not to be construed as limiting the scope of the subject invention.
  • the electrical test parameters of the bipolar transistors having arsenic emitters are similar to the bipolar transistors having phosphorus emitters.
  • the bipolar transistors prepared in accordance with the present invention can be modified to provide other types of semiconductor devices having arsenic emitters.
  • Examples of semiconductor devices which can be fabricated from the bipolar transistors prepared in accordance with the process hereinbefore described with reference to Figs. 1-8 are a Schottky transistor, a capacitor, an implant resistor and a lateral PNP transistor. The fabrication of such semiconductor devices will now be described with reference to Figs. 9-12.
  • a Schottky transistor is formed by opening a window 80 in the silicon dioxide layers 50 and 24 of the wafer 14 so as to expose a portion 82 of the base region 36 and the upper surface of the epitaxial layer 22. Then just prior to the metallization steps of the wafer 14 as heretofore described, the following steps are performed: (a) platinum is sputtered onto the wafer 14; (b) the wafer 14 is heat treated to form platinum silicide on the portion 82 of the base region 36 and the epitaxial layer 22; (c) unreacted platinum is removed so that only the platinum silicide remains on the portion 82 of the base region 36 and the epitaxial layer 22; and (d) titanium and tungsten are sputtered onto the wafer 14 to form a bonding layer between the platinum silicide and the subsequently applied metal layer.
  • a heavily doped N+ region 90 is formed by implantation of the epitaxial layer 22 during the implantation of the collector contact region 34 of the wafer 14. After the silicon dioxide layer 56 is
  • silicon dioxide layers 50 and 56 are etched away, leaving only a thin layer of silicon dioxide 92.
  • Metal contacts 94 and 96 are then formed at the same time the metal contacts 70, 72, 74 and 76 are formed on the wafer 14.
  • the capacitor thus consists of contact 94 as one connection, contact 96 and N+ regions 90 and 93 as the other connection, and layer 92 as the dielectric.
  • resistors may also be constructed from the wafer 14 prepared in accordance with the process of the present invention.
  • two heavily doped P+ regions 100 and 102 are formed by implantation into the epitaxial layer 22 during the implantation of the base region 36 in the wafer 14.
  • the P+ region 104 is separately implanted with boron atoms to form the resistive element of the resistor. Regions 100 and 102 and their respective metal contacts form the connections to the resistor.
  • the wafers 14 prepared in accordance with the process of the present invention may also be used to fabricate lateral PNP transistors.
  • heavily doped P+ regions 110 and 112 are formed by implantation during the formation of the base region 36.
  • a heavily doped N+ region 114 is formed by implantation during the formation of the emitter region 66 of the wafer 14.
  • metal contacts 116, 118, and 120 are formed to provide ohmic contact with the P+ regions 110, 112 and the N+ region 114.
  • the P+ regions 110 and 112 form the emitter and collector of the PNP transistor; the epitaxial layer 22 is the base of the transistor; and the N+ region 114 and contact 120 function as the base contacts.

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Abstract

A fabrication process for bipolar transistors having arsenic emitters which include masking an epitaxial layer so as to provide windows for defining a collector contact region, a base region and an isolation region. Phosphorus ions are introduced into the epitaxial layer through the window defining the collector contact region; and boron ions are introduced into the epitaxial layer through the windows defining the base region and the isolation region. The epitaxial layer is also masked to provide a window defining an emitter region within the base region and windows for ohmic connections to the base region, the collector contact region and the isolation region. Arsenic ions are then introduced into the epitaxial layer through the window defining the emitter region; and electrical connections are provided to the emitter region, the base region, the collector region and the isolation region through the windows for ohmic connections.

Description

PROCESS FOR FABRICATING SEMICONDUCTOR
DEVICES HAVING ARSENIC EMITTERS
Background of the Invention
1. Field of the Invention
The present invention relates to a process for fabricating semiconductor devices, and more particularly but not by way of limitation, to a process for fabricating semiconductor devices having arsenic emitters.
2. Description of the Prior Art
An NPN transistor is a fundamental circuit element of bipolar integrated circuits. Structurally, a bipolar NPN transistor has an N type collector and an N type emitter separated by a P type base. The collector is an island of N type material located on top of a P type substrate; the base region is an island of P type material located within the collector region; and the emitter is an island of N type material located within the base. Electrical contacts are provided to the collector, the emitter and the base. A low resistivity layer is located under the base and collector contacts so as to minimize the internal resistance of the collector. The collector region, which is an N type
epitaxial layer formed on the top of the P type substrate, is isolated from adjacent devices by a P type isolation region or a region of silicon dioxide.
An important consideration in the fabrication of semiconductor devices is circuit density. Higher circuit density allows more devices to be fabricated on a single wafer, thereby lowering the cost of individual circuits. Factors adversely affecting circuit density are lateral diffusion of doped regions and mask alignment.
NPN transistors having phosphorus emitters have heretofore been employed in an effort to provide semiconductor devices having improved circuit density. However, one major concern in the fabrication of NPN transistors having phosphorus emitters is the beta variations which occur across the wafer. These beta variations are believed to be due to the temperature variation which occur across the wafer during the fabrication process. That is, at low diffusion temperatures the diffusion coefficients for phosphorus vary, thereby resulting in varying emitter-base pinch resistances and consequently varying beta values.
Therefore, a need exists for a high yield process for fabricating bipolar transistors which substantially eliminates beta variations across the wafer without sacrificing high current gain and breakdown voltages, high frequency response, high signal to noise ratio and circuit density. It is to such a process that the present invention is directed.
Summary of the Invention
According to the present invention, a process is provided for fabricating a bipolar transistor in a wafer. The wafer is a semiconductor structure that includes a silicon substrate of a first conductivity type, an epitaxial layer of a second conductivity type and a buried layer of the second conductivity type disposed between a portion of the substrate and the epitaxial layer. The process includes the steps of:
(1) masking the epitaxial layer of the wafer so as to provide windows for defining a collector contact region, a base region and an isolation region in the epitaxial layer;
(2) masking the windows defining the base region and the isolation region;
(3) introducing arsenic ions into the collector contact region of the epitaxial layer through the window defining the collector contact region;
(4) masking the windows defining the collector contact region and the base region;
(5) introducing aluminum ions into the epitaxial layer through the window defining the isolation region;
(6) masking the window defining the collector contact region;
(7) introducing boron ions into the epitaxial layer through the windows defining the base region and the isolation region; (8) masking the epitaxial layer of the wafer so as to provide a window for defining an emitter region within the base region and windows for providing ohmic connections to the base region, the collector contact region and the isolation region;
(9) masking at least the windows defining the ohmic connections to the base region and isolation region;
(10) introducing arsenic ions into the emitter region of the epitaxial layer through the window defining the emitter region; and
(11) forming electrical connections to the emitter region, the base region, the collector region and the isolation region through the window defining the emitter region and the windows for providing the ohmic connections to the base region, the collector contact region and the isolation region of the epitaxial layer.
An important aspect of the present invention is that the bipolar transistors produced employing arsenic ions and boron ions as conductive type impurities do not suffer from beta variation across the wafer and yet yield substantially the same base, emitter and emitter-base pinch resistances as bipolar transistors employing phosphorus ions as one of the conductive type impurities. That is, the bipolar transistors produced in accordance with the process of the present invention wherein arsenic and boron ions are employed as conductive impurities possess similar electrical characteristics as bipolar
transistors produced using phosphorus process technology; but the bipolar transistors produced in accordance with the process of the present invention do not suffer from the beta variations across the wafers as do bipolar transistors produced using phosphorus process technology.
Accordingly, an object of the present invention is to provide a bipolar transistor in a wafer which possesses
desirable electrical characteristics and which does not suffer from beta variations across the wafer.
Another object of the present invention, while achieving the above-stated object, is to provide an improved process for fabricating a bipolar transistor in a wafer having a silicon substrate of a first conductivity type, an epitaxial layer of a second conductivity type and a buried layer of the second conductivity type disposed between a portion of the substrate and the epitaxial layer.
Other objects, features and advantages of the present invention will become apparent from the following detailed description when read in conjunction with the drawings and appended claims.
Brief Description of the Drawings
FIG. 1 is a diagrammatical cross-sectional view of a wafer after formation of a buried layer in a process for fabricating an NPN transistor according to the present invention.
FIG. 2 is a diagrammatical cross-sectional view of the wafer after formation of openings in a first oxide layer to define a collector contact region, a base region and an emitter region.
FIG. 3 is a diagrammatical cross-sectional view of the wafer after implantation of the collector contact region.
FIG. 4 is a diagrammatical cross-sectional view of the wafer after implantation of the isolation region.
FIG. 5 is a diagrammatical cross-sectional view of the wafer after implantation of the base region.
FIG. 6 is a diagrammatical cross-sectional view of the wafer after deposition of a second oxide layer and formation of openings in the second oxide layer to define an emitter region and ohmic contact region.
FIG. 7 is a diagrammatical cross-sectional view of the wafer after implantation of the emitter region.
FIG. 8 is a diagrammatical cross-sectional view of the wafer after deposition and patterning of a metallization layer.
FIG. 9 is a diagrammatical cross-sectional view of a Schottky transistor fabricated in accordance with the process of the present invention.
FIG. 10 is a diagrammatical cross-sectional view of a capacitor fabricated in accordance with the process of the present invention.
FIG. 11 is a diagrammatical cross-sectional view of an implant resistor fabricated in accordance with the process of the present invention.
FIG. 12 is a diagrammatical cross-sectional view of a lateral PNP transistor fabricated in accordance with the process of the present invention.
Detailed Description
The present invention relates to a process for fabricat- ing integrated circuits having bipolar transistors and other circuit elements. The process for fabricating NPN bipolar transistors is described in detail hereinafter with reference to FIGS. 1-8.
Referring now to FIG. 1, a P type silicon substrate 12 is illustrated. The silicon substrate 12 has a crystallographic orientation of <111>, as designated by Miller indices, and a resistivity in the range of 1.5 to 3.0 ohm-centimeters. The surface of the silicon substrate 12 is desirably positioned 4.5 degrees off the <111> direction toward the nearest <110> direction. Such substrates are commonly used for the fabrication of bipolar devices.
The term "substrate" as used herein refers to the P type region of silicon upon and partially within which the integrated circuits are fabricated; and the term "wafer" includes the substrate and the features and elements fabricated on top of the substrate.
The wafer 14 is first thermally oxidized to form a layer of silicon dioxide (oxide) 16 on a upper surface of the silicon substrate 12. An oxide thickness of approximately 8000 Angstroms is preferred.
Using a first mask, a first masking layer (not shown) is deposited over a portion of the substrate 12 so that a window 18 is opened in the silicon dioxide layer 16 to enable formation of a buried layer. This is desirably done
photolithographically by the sequential steps of: (a) coating the substrate 12 with a layer of photoresist; (b) exposing the photoresist using a buried layer mask; (c) developing the photoresist to expose a portion of the silicon dioxide layer 16; (d) etching the exposed silicon dioxide layer 16 down to the substrate 12; and (e) stripping the remaining photoresist from the substrate 12. Thus, the substrate 12 has a portion exposed through the window 18 in the silicon dioxide layer 16.
An N type impurity, preferably antimony, is then
implanted into the P substrate to form a heavily doped N+ buried layer 20. The buried layer 20 will later serve as a heavily doped portion of a collector of an NPN transistor. After forming the buried layer 20, the silicon dioxide layer 16 is removed by etching in hydrofluoric acid.
As illustrated in FIG. 2, dichlorosilane is then applied to the substrate 12 so as to form an epitaxial layer 22 on the top of the buried layer 20 and the substrate 12. The epitaxial layer 22 is lightly doped N conductivity and has the same crystallographic orientation as the substrate 12. The thickness and resistivity of the epitaxial layer 22 will affect the operational characteristics of the transistor, e.g. gain and breakdown voltage. For an NPN transistor having an operational voltage of 15 volts and breakdown voltage of 35 volts, the thickness of the epitaxial layer 22 is desirably between 2.5 and 3.1 microns and the resistivity is between 0.7 and 1.1 ohm-centimeters, with the optimum values in the center of each range. If the resistance falls outside the range, either the breakdown voltage or the gain of the transistor will decrease to unacceptable levels. In the formation of the epitaxial layer 22 suitable results have been obtained wherein chemical vapor techniques are employed using arsine as a dopant. The concentration of the arsine (i.e. the dopant) controls the resistivity of the resulting epitaxial layer 22.
The top surface of the epitaxial layer 22 is then oxidized to form a layer of silicon dioxide 24. The silicon oxide layer 24 is grown by placing the wafer 14 in an oxidizing atmosphere at an elevated temperature. Preferably the epitaxial layer 22 is oxidized until the silicon dioxide layer 24 is provided with a nominal thickness of approximately 1000 Angstroms.
If desired, a layer of silicon nitride 26 can be deposited on top of the silicon dioxide layer 24 by use of low pressure chemical deposition. The silicon nitride layer 26, which improves the resolution of later oxide etching steps in the fabrication of a bipolar transistor in the wafer 14, preferably has a nominal thickness of approximately 2800 Angstroms.
Windows 28, 30 and 32 are defined in the silicon dioxide and silicon nitride layers 24, 26, respectively, by a first masking layer 33 formed over selected portions of the silicon nitride layer 26 by application of a first mask.
Formation of the windows 28, 30 and 32 exposes the upper surface of the epitaxial layer 22 to define a collector contact region 34, a base region 36 and an isolation region 38. The isolation region 38 encircles the collector contact region 34, the base region 36 and the buried layer 20. By defining all three regions with a single mask, the positions of the three regions are self-aligned with respect to each other. This eliminates the need to compensate for mask alignment tolerances, and thereby increases circuit density. In subsequent processing steps which will be described hereinafter, certain regions will be masked by masking selected layers during ion implantation of the other regions of the wafer 14.
Once the windows 28, 30 and 32 have been formed in the upper surface of the epitaxial layer 22, the exposed areas of the epitaxial layer 22 are oxidized (see FIG. 3). The oxidation of the exposed areas of the epitaxial layer 22 is achieved by thermally growing a layer of silicon dioxide 40 to a nominal thickness of about 1000 Angstroms. Thus, subsequent ion implantation of the collector contact region 34 and isolation region 38 can be performed through the silicon dioxide layer 40 and the problem of ion channeling is substantially alleviated.
After the exposed areas of the epitaxial layer 22 have been thermally oxidized to provide the desired silicon diox- ide layer 40, a second masking layer 42 is deposited over the base region 36 and the isolation region 38 by application of a second mask. In order to form the second masking layer 42 the upper surface of the wafer 14 is coated with a layer of photoresist material; and the photoresist material is then developed by exposing the photoresist material through a mask. After developing, the second masking layer 42 covers the base and isolation regions 34 and 36, while the collector contact region 32 remains exposed. The second masking layer 42 is oversized with respect to the base and isolation regions 36, 38. Thus, the alignment of the second masking layer 42 with respect to the wafer 14 is not
critical, provided the alignment of the second masking layer 42 is sufficiently precise to insure that the collector contact region 34 is exposed while the base region 36 and the isolation region 38 are covered.
The collector contact region 34 is then implanted to form a heavy doped N+ region 44. Phosphorus atoms are implanted through the silicon oxide layer 40 at an implantation energy of about 80 KeV and at a dosage sufficient to provide about 1 e+15 atoms of arsenic per square centimeter. The wafer 14, at this step in the process, is illustrated in FIG. 3. The resulting heavily doped N+ region 44 does not extend all the way down to the N+ buried layer 20.
The isolation region 38 is thereafter doped and the collector contact region 34 and the base region 36 are masked using the following procedures. The second masking layer 42 is removed; and a third masking layer 46 of photoresist material is formed over the collector contact and base regions 34, 36 as illustrated in FIG. 4. A portion of the third masking layer 46 is partially removed to expose the isolation region 38. The alignment of the third masking layer 46 is not critical because the third masking layer 46 is oversized.
The isolation region 38 is then ion implanted through the silicon dioxide layer 40 with aluminum ions to form a heavily doped P+ region 48. While the implantation energy and dosage of the aluminum ions are not critical, desirable results can be obtained when the implantation energy employed to implant the aluminum ions is about 120 KeV and the dosage of the aluminum ions is sufficient to provide about 5 e-H4 atoms of aluminum per square centimeter.
After implantation of the aluminum ions the collector contact region 34 and the isolation region 38 are annealed so that diffusion of the aluminum ions occurs. Such is accomplished by removing the third masking layer 46 and thereafter heating the wafer 14 to an elevated temperature of about 1000 degrees Celsius in a nitrogen atmosphere for a period of from about 175 to about 195 minutes in a diffusion furnace. At the elevated temperature, annealing occurs to repair crystal lattice damage caused by ion implantation. Diffusion of the dopant ions also occurs, causing the doped regions to expand. The collector contact region 34, the isolation region 38 and the buried N+ region 20 all expand in size. However, at this point, the P-f doped isolation region 38 has not yet joined with the P substrate 12 to complete the electrical isolation of the transistor. A subsequent diffusion step is employed to join the P+ doped isolation region 38 and the P substrate 12.
One important aspect of the present invention is the use of aluminum doped isolation. Well known oxide isolation is not practical because of the relatively thick epitaxial layer used in linear transistors. Boron doped isolation results in excessive lateral diffusion because of the combination of the slow diffusivity of boron and the thickness of the epitaxial layer through which the dopant must diffuse. Two advantages of using aluminum as a dopant are: (1) the total time in the diffusion furnace is reduced as compared to boron doped isolation and, as a result, upward diffusion of the buried layer is reduced, enabling use of a much thinner epitaxial layer; and (2) lateral diffusion is reduced thereby permitting circuit elements to be more closely spaced, thus increasing circuit density.
It may be desirable to remove the layer of silicon dioxide 40 so that a thicker layer of silicon dioxide 50 may be provided. The thicker silicon dioxide layer 50 better protects the surface of the epitaxial layer 22 during a subsequent etching step. It is desirable that the thicker silicon dioxide layer 50 be thermally formed to a nominal thickness of about 1000 Angstroms. Alternatively, another option is to oxidize the silicon dioxide layer 40 to form an additional 350 Angstroms to the existing 650 Angstroms of the silicon dioxide layer 40. Of course, one may continue with only the initial silicon dioxide layer 40, but at the added risk of damaging the emitter region during subsequent dry etching.
As shown in FIG. 5, the next steps of the process involve doping the base region 36 while masking the collector contact region 34. A fourth masking layer 52 of photoresist is formed (using a fourth mask) which covers the collector contact region 34, while maintaining the base region 36 and the isolation region 38 in an exposed
condition. Boron ions are then implanted through the thicker silicon dioxide layer 50 and into the base region 36 and the isolation region 38 at an implant energy of about 35 Kev and at a dosage of about 3.1 e+14 atoms of boron per square centimeter so as to create a heavily doped P+ region 54, while increase the buried P+ region 48 by doping of the isolation region 38. The base region 36 is fully doped by this implantation step so that a subsequent implantation is not required. As an option, the isolation region 38 may be masked to prevent implantation of boron ions into the isolation region 38.
The implanted base region 36 and the implanted isolation region 38 are then annealed and diffused in a nitrogen atmosphere by placing the wafer 14 in a furnace maintained at a temperature of about 1000 degrees Celsius for a period of from about 175 to about 195 minutes. At this elevated temperature, all the doped regions increase in size. In addition, the crystal lattice in the base and isolation regions 36, 38 are annealed to repair implantation damage. As illustrated in FIG. 5, this diffusion step causes the P+ region 48 to diffuse downward so that the isolation region 38 and the P substrate 12 are united, thereby isolating the portion of the epitaxial layer 22 in which the transistor is formed.
The layer of silicon nitride 26 is then removed to expose the silicon dioxide layer 50. This may be accomplished by etching using hot phosphoric acid. As an
optional next step, a small amount of arsenic can be
implanted through silicon dioxide layer 50 and into the upper surface of the epitaxial layer 22. This implantation acts to adjust the field threshold, and is necessary only if surface inversion problems occur.
Referring now to FIG. 6, a layer of silicon dioxide 56 is deposited on top of silicon dioxide layer 50. Any oxide deposition process that is performed at a temperature of about 750 degrees Celsius or less may be used. However, desirable results can be obtained when a low temperature oxide (LTO) process is used at a temperature of about 420 degrees Celsius to deposit about 4000 Angstroms of silicon dioxide. The low temperature of the process prevents the formation of defects in the base region 36 which would occur at a higher temperature.
A fifth masking layer (not shown) is deposited over the silicon dioxide layer 56 by application of a fifth mask so that windows 58, 60, 62 and 64 are defined in silicon dioxide layers 50 and 56. The windows 58, 60 and 62 expose areas of the isolation region 38, the collector contact region 34 and the base region 36 to be used as ohmic
contacts; and the window 64 exposes an area of the base region 36 defining an emitter region 66 (see FIG. 7) in which an emitter will be formed. The portions of the silicon dioxide layers 50, 56 which are within the confines of the windows 58, 60, 62 and 64 are then etched away, leaving the wafer 14 as shown in FIG. 6.
Referring now to FIG. 7, the emitter region 66 is doped while masking the base region 36 and the isolation region 38. A sixth masking layer 68 of photoresist is formed using a sixth mask covering the isolation region 38 and the base region 36, with the collector contact region 34 and the emitter region 66 exposed. Arsenic ions are then implanted into the emitter region 66 and the collector contact region 34 at an implant energy of about 50 KeV and at a dosage of about 7.5 e+15 atoms of arsenic per square centimeters so as to create a heavily doped N+ region and to add to the doping of the collector contact region 34. As an option, the collector contact region 34 may be covered by the sixth masking layer 68 to prevent further implantation. When the desired implantation of the arsenic ions has been achieved, the sixth masking layer 68 is stripped, and the implanted regions annealed by heating the wafer 14 to a temperature of about 1000 degrees Celsius for a period of time of from about 240 to about 270 minutes in a nitrogen atmosphere.
The balance of the process relies upon conventional metallization steps. A first metal layer is deposited, then patterned by well known masking and etching processes, then alloyed to establish good contact with the underlying silicon substrate 12. Thus, the wafer 14 illustrated in FIG. 8 includes metal contact 70, 72, 74 and 76, which are respectively connected to the silicon substrate 12, the collector contact region 34, the base region 36, and the emitter region 66.
If it is desirable to form a second layer of metal connections, a layer of silicon dioxide is deposited over the first metal layer so as to insulate the second metal layer from the first metal layer. Windows are then opened in the silicon oxide layer and the second metal layer deposited. The metal is patterned by another masking process, and then alloyed. A passivation oxide is deposited on top of the wafer 14 and then windows are opened to external contact pads. The wafer 14 is now ready for dicing.
The process for fabricating a bipolar transistor described above with reference to Figs. 1-8 was simulated using a ID process simulator SUPREM-3 and a 2D device simulator PISCES -2B. In addition to the target values for the process, other factors taken into considerations were the capability of isolation at the top end of the epitaxial specification the ability to maintain the implant resistor sheet resistivity. Ramping of the wafer during both base diffusion and emitter diffusion was from 800 degrees Celsius and the target value for the base width was 4500 Angstroms.
The values obtained from the resultant optimization are set forth in Table I.
Table I
Base implant Emitter Implant
Dose: 3.85 e+14 Dose: 7.39e+15
Energy: 27 KeV Energy: 48 KeV
Base Diffusion Emitter Diffusion
Top temperature: 976 C. Top temperature: 996 C. Soak time: 211 min. Soak time: 197 min. The impact of the process of the present invention on isolation and resistor resistivity was then investigated. It was determined that isolation was achieved at the top end of the epitaxial thickness specification for aluminum implant energies of 80 KeV and 120 KeV. The implant resistor was, however, found to have decreased to 1.55
kohms/square, and that its depth had increased from 0.321um to 0.656 um due to increased drive times at base and emitter. An optimization to re-target for 2kOhms/square was performed and the resistivity was recovered by lowering the dose from 2.9e+13 to 2.05e+13. It was also determined that there was no substantial difference when implanting was carried out at an implant energy of either 40 KeV or 44 KeV.
A comparison of the resistivities and xj's of a phosphorus emitter prepared in accordance with the process disclosed in U.S. Patent 4,648,909 and an arsenic emitter prepared in accordance with the process of the present invention are set forth in Table II. Table II
Parameter Phosphorus emitter Arsenic Emitter
Base xj (urn) .88 1.053 Base Res. (Ohms/sq) 369 371 Emitter xj (urn) .665 .602 Base under Emitter 1.11 1.049 Emitter Res. (Ohms/sq) 19.6 19.6 Base Width (um) .445 .447 Gummel No. (No./sq.cm) 34e+12 4.33e+12 Rpinch (Ohms/sq) 7561 7554
Imp Resistor (Ohms/sq) 1988 2027 Buried layer (Ohms/sq) 23 22.84 Epitaxy (Ohms/sq) 2567 2491 Sinker/Plug (Ohms/sq) 18.1 17.7 A comparison of beta and LVceo for a phosphorus emitter prepared in accordance with the process disclosed in U.S. Patent 4,648,909 and an arsenic emitter prepared in accordance with the process of the present invention was performed using the 2D device simulator PISCES-2B. The results are set forth in Table III.
Table III
Parameter Phosphorus Emitter Arsenic Emitter NPN Beta 62 71
NPN LVceo 15.5 15.4 it should be noted that the beta increases by approximately 15% as a consequence of the arsenic emitter. This could be easily fine tuned at the emitter diffusion process. However, the LVceo of the two emitters is substantially the same. Analysis of the above data indicates that the difference in the NPN Beta parameter of the two emitters is due to avalanche (emitter acceleration) which is driven to some degree by beta.
In order to further illustrate the process of the present invention for fabricating a bipolar transistor having an arsenic emitter the following example is given. However, it is to be understood that the example is for illustrative purposes only and is not to be construed as limiting the scope of the subject invention. Example
Five (5) silicon wafers having arsenic epitaxy were processed in accordance with the process of the present invention. At emitter diffusion the initial wafer, which had a soak time of 197 minutes, gave a beta of 160. The soak time for the remaining silicon wafers was reduced to 180 minutes and the beta on the remaining wafers was 120 and the LVceo' s of such wafers were 18-19 volts. A typical beta for a silicon wafer having a phosphorus emitter is approximately 100 and the LVceo is about 18 volts. It should be noted that the beta and LVceo measurements on the bipolar transistors having arsenic emitters were made after emitter diffusion and such measurements were not determined by electrical test procedures.
Properties of bipolar transistors having arsenic emitters fabricated in accordance with the process of the present invention were then compared with similar properties of bipolar transistors having a phosphorus emitters. The resulting comparative data is as follows:
Parameter Arsenic emitter Phosphorus emitter
Rho Sink 20.9 22
Rho Epitaxy 3.45k 2.7k
Rho Emitter 2.42 2.5
Rho Implant 2k 2.03k Rho Base 339 374
Iso Diode 63.1 62.7
NPN4SBlm 90 90
With the exception of the Rho epitaxy and the Rho base, the electrical test parameters of the bipolar transistors having arsenic emitters are similar to the bipolar transistors having phosphorus emitters.
The bipolar transistors prepared in accordance with the present invention can be modified to provide other types of semiconductor devices having arsenic emitters. Examples of semiconductor devices which can be fabricated from the bipolar transistors prepared in accordance with the process hereinbefore described with reference to Figs. 1-8 are a Schottky transistor, a capacitor, an implant resistor and a lateral PNP transistor. The fabrication of such semiconductor devices will now be described with reference to Figs. 9-12.
Referring now to FIG. 9, a Schottky transistor is formed by opening a window 80 in the silicon dioxide layers 50 and 24 of the wafer 14 so as to expose a portion 82 of the base region 36 and the upper surface of the epitaxial layer 22. Then just prior to the metallization steps of the wafer 14 as heretofore described, the following steps are performed: (a) platinum is sputtered onto the wafer 14; (b) the wafer 14 is heat treated to form platinum silicide on the portion 82 of the base region 36 and the epitaxial layer 22; (c) unreacted platinum is removed so that only the platinum silicide remains on the portion 82 of the base region 36 and the epitaxial layer 22; and (d) titanium and tungsten are sputtered onto the wafer 14 to form a bonding layer between the platinum silicide and the subsequently applied metal layer.
The steps required to fabricate a capacitor from the wafer 14 prepared in accordance with the process of the present invention will now be described with reference FIG. 10. In the fabrication of a capacitor, a heavily doped N+ region 90 is formed by implantation of the epitaxial layer 22 during the implantation of the collector contact region 34 of the wafer 14. After the silicon dioxide layer 56 is
deposited, the silicon dioxide layers 50 and 56 are etched away, leaving only a thin layer of silicon dioxide 92.
Metal contacts 94 and 96 are then formed at the same time the metal contacts 70, 72, 74 and 76 are formed on the wafer 14. The capacitor thus consists of contact 94 as one connection, contact 96 and N+ regions 90 and 93 as the other connection, and layer 92 as the dielectric.
As previously stated, resistors may also be constructed from the wafer 14 prepared in accordance with the process of the present invention. As shown in FIG. 11, two heavily doped P+ regions 100 and 102 are formed by implantation into the epitaxial layer 22 during the implantation of the base region 36 in the wafer 14. The P+ region 104 is separately implanted with boron atoms to form the resistive element of the resistor. Regions 100 and 102 and their respective metal contacts form the connections to the resistor.
The wafers 14 prepared in accordance with the process of the present invention may also be used to fabricate lateral PNP transistors. As shown in FIG. 12 heavily doped P+ regions 110 and 112 are formed by implantation during the formation of the base region 36. A heavily doped N+ region 114 is formed by implantation during the formation of the emitter region 66 of the wafer 14. Later, metal contacts 116, 118, and 120 are formed to provide ohmic contact with the P+ regions 110, 112 and the N+ region 114. Thus, the P+ regions 110 and 112 form the emitter and collector of the PNP transistor; the epitaxial layer 22 is the base of the transistor; and the N+ region 114 and contact 120 function as the base contacts.
From the above description, it is apparent that the invention disclosed herein provides a novel and advantageous process for fabricating integrated circuits having bipolar junction transistors and other circuit elements. While presently preferred embodiments of the invention have been described for purposes of this disclosure, numerous changes may be made which will readily suggest themselves to those skilled in the art and which are encompassed within the spirit of the invention disclosed and as defined in the appended claims.

Claims

What is claimed is:
1. A process for fabricating a bipolar transistor in a wafer having a silicon substrate of a first conductivity type, an epitaxial layer of a second conductivity type and a buried layer of the second conductivity type disposed between a portion of the substrate and the epitaxial layer, the process comprising:
masking the epitaxial layer of the wafer so as to provide windows for defining a collector contact region, a base region and an isolation region in the epitaxial layer;
masking the windows defining the base region and the isolation region;
introducing phosphorus ions into the collector contact region of the epitaxial layer through the window defining the collector contact region;
masking the windows defining the collector contact
region and the base region;
introducing aluminum ions into the epitaxial layer
through the window defining the isolation region; masking the window defining the collector contact
region;
introducing boron ions into the epitaxial layer through the windows defining the base region and the isolation region;
masking the epitaxial layer of the wafer so as to provide a window for defining an emitter region within the base region and windows for providing ohmic connections to the base region, the collector contact region and the isolation region;
masking at least the windows defining the ohmic connections to the base region and isolation region;
introducing arsenic ions into the emitter region of the epitaxial layer through the window defining the emitter region; and
forming electrical connections to the emitter region. the base region, the collector region and the isolation region through the window defining the emitter region and the windows for providing the ohmic connections to the base region, the collector contact region and the isolation region of the epitaxial layer.
2. The process for fabricating a bipolar transistor of claim 1 further comprising oxidizing the epitaxial layer exposed through the windows to form a layer of silicon dioxide prior to masking the windows defining the base region and the isolation region.
3. The process for fabricating a bipolar transistor of claim 1 wherein step of masking the epitaxial layer of the wafer further includes providing a window defining a capacitor region in the epitaxial layer and wherein the process for fabricating a bipolar transistor further comprises introducing arsenic ions into the epitaxial through the window defining the capacitor region during the introduction of the arsenic ions into the epitaxial layer via the window defining the collector contact region.
4. The process for fabricating a bipolar transistor of claim 1 wherein the epitaxial layer has a thickness of between 2.5 and 3.1 microns, a resistivity of between 0.7 and 1.1 ohm centimeters.
5. The process for fabricating a bipolar transistor of claim 1 wherein the masking of the epitaxial layer of the wafer comprises the steps of:
forming a layer of silicon dioxide on the epitaxial
layer; and
forming a layer of silicon nitride on the layer of the silicon dioxide.
6. The process for fabricating a bipolar transistor of claim 5 wherein masking the epitaxial layer so as to provide the window defining the emitter region comprises:
forming at least one layer of silicon dioxide on the
epitaxial layer.
7. The process for fabricating a bipolar transistor of claim 6 wherein the phosphorus ions are introduced into the collector contact region of the epitaxial layer at an energy of about 80 KeV and at a dosage of about 1 e+15 atoms per square centimeter.
8. The process for fabricating a bipolar transistor of claim 7 wherein the boron ions are introduced into the base region and the isolation region of the epitaxial layer at an energy of about 35 KeV and at a dosage of 3.1 e+14 atoms per square centimeter.
9. The process for fabricating a bipolar transistor of claim 8 wherein the arsenic ions are introduced into the emitter region of the epitaxial layer at an energy of about 50 KeV and at a dosage of about 7.5 e+15 atoms per square centimeter.
10. A process for fabricating a bipolar transistor in a wafer having silicon substrate of a first conductivity type, an epitaxial layer of a second conductivity type and a buried layer of the second conductivity type disposed between a portion of the substrate and the epitaxial layer, the process comprising:
masking the epitaxial layer of the wafer so as to provide windows for defining a collector contact region, a base region and an isolation region;
oxidizing the portions of the epitaxial layer exposed through the windows so as to provide a layer of insulating material over the exposed portions of the epitaxial layer;
masking the windows defining the base region and the
isolation region;
introducing phosphorus ions into the collector contact region of the epitaxial layer through the collector contact window at an energy of about 80 KeV and at a dosage of about 1 e+15 atoms per square centimeter;
masking the windows defining the collector contact
region and the base region;
introducing aluminum ions into the epitaxial layer
through the window defining the isolation region; masking the window defining the collector contact
region;
introducing boron ions into the base region and the isolation region of the epitaxial layer via the windows defining the base region and the isolation region at an energy of about 35 KeV and at a dosage of about 3.1 e+14 atoms per square centimeter;
masking the epitaxial layer of the wafer so as to provide a window for defining an emitter region within the base region and windows for providing ohmic connections to the base region, the collector contact region and the isolation region;
masking at least the windows for ohmic connections to the base region and isolation region;
introducing arsenic ions into the epitaxial layer
through the window defining the emitter region at an energy of about 50 KeV and at a dosage of about 7.5 e+15 atoms per square centimeter; and forming electrical connections to the emitter region, the base region, the collector region and the isolation region through the windows defining such regions.
11. The process for fabricating a bipolar transistor of claim 10 wherein the insulating material formed on the portion of the epitaxial layer exposed through the windows is silicon dioxide.
12. The process for fabricating a bipolar transistor of claim 10 wherein step of masking the epitaxial layer of the wafer further includes providing a window defining a capacitor region in the epitaxial layer and wherein the process for fabricating a bipolar transistor further comprises introducing phosphorus ions into the epitaxial through the window defining the capacitor region during the introduction of the arsenic ions into the epitaxial layer via the window defining the collector contact region.
13. The process for fabricating a bipolar transistor of claim 10 wherein the epitaxial layer has a thickness of between 2.5 and 3.1 microns, a resistivity of between 0.7 and 1.1 ohm centimeters.
14. The process for fabricating a bipolar transistor of claim 10 wherein the masking of the epitaxial layer of the wafer comprises the steps of:
forming a layer of silicon dioxide on the epitaxial
layer; and
forming a layer of silicon nitride on the layer of the silicon dioxide.
15. The process for fabricating a bipolar transistor of claim 13 wherein the step of forming the second mask comprises:
forming at least one layer of silicon dioxide on the epitaxial layer.
16. A process for fabricating a bipolar transistor in a wafer having a silicon substrate of a first conductivity type, an epitaxial layer of a second conductivity type and a buried layer of the second conductivity type disposed between a portion of the substrate and the epitaxial layer, the method comprising:
masking the epitaxial layer with a first mask having
openings therein for providing windows defining a collector contact region, a base region and an isolation region in the epitaxial layer;
oxidizing the epitaxial layer exposed through the windows to provide a layer of silicon dioxide on the portion of the epitaxial layer exposed through such windows;
masking the windows defining the base region and the isolation region with a second mask of a photoresist material;
developing the photoresist material;
introducing phosphorus ions into the epitaxial layer through window defining the collector contact region at an implant energy of about 80 KeV and at a dosage of about 1 e+15 atoms per square centimeter;
removing the second mask;
masking the windows defining the collector contact
region and the base region with a third mask;
removing a portion of the third mask so as to expose the isolation region;
introducing aluminum ions into the epitaxial layer
through the window defining the isolation region to form a heavily doped P+ region in the epitaxial layer;
removing the third mask;
heating the wafer to a temperature effective to anneal and diffuse the collector contact region and the isolation region and thereby repair crystal lattice damage resulting from ion implantation while also expanding the size of the collector contact region, the isolation region and the buried P+ region;
masking the window defining the collector contact region with a fourth mask;
introducing boron ions into the epitaxial layer through the windows defining the base region and the isolation region at an implant energy^ of about 35 KeV and at a dosage of about 3.1 e+14 atoms per square centimeter;
heating the wafer to a temperature effective to anneal and diffuse the implanted base region and the implanted isolation region and thereby repair crystal lattice damage resulting from ion implantation while also expanding the size of the implanted base region, the implanted isolation region and the P+ region so that the P+ region and the P substrate are united and thereby isolate a portion of the epitaxial layer;
masking the epitaxial layer with a fifth mask having
openings therein for providing windows defining an emitter region within the base region and openings for providing ohmic connections to the base region, the collector contact region and the isolation region;
masking at least the windows for providing ohmic connections to the base region and the isolation region; introducing arsenic ions into the epitaxial layer
through the windows for the emitter region and the collector contact region defined by the fifth mask at an implant energy of about 50 KeV and at a dosage of about 7.5 e+15 atoms per square centimeter; removing the fifth mask;
heating the wafer to a temperature effective to anneal and diffuse the emitter region and the collector contact region and thereby repair crystal lattice damage resulting from ion implantation;
forming electrical connections to the emitter region, the base region, the collector region and the isolation region.
PCT/US1994/007682 1993-07-12 1994-07-08 Process for fabricating semiconductor devices having arsenic emitters WO1995002898A1 (en)

Priority Applications (3)

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KR1019960700076A KR960704351A (en) 1993-07-12 1994-07-08 PROCESS FOR FABRICATING SEMICONDUCTOR DEVICES HAVING ARSENIC EMITTERS
EP94923385A EP0710399A1 (en) 1993-07-12 1994-07-08 Process for fabricating semiconductor devices having arsenic emitters
JP7504626A JPH09500760A (en) 1993-07-12 1994-07-08 Manufacturing process of semiconductor device with arsenic implanted emitter

Applications Claiming Priority (2)

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US9051693A 1993-07-12 1993-07-12
US08/090,516 1993-07-12

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EP0818055A1 (en) * 1995-03-27 1998-01-14 Micrel Incorporated Self-alignment technique for semiconductor devices
CN104992966A (en) * 2015-05-21 2015-10-21 中国电子科技集团公司第十三研究所 Manufacturing method of bipolar high-frequency power transistor chip low in thermal budget

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EP0035126A2 (en) * 1980-03-03 1981-09-09 International Business Machines Corporation Bipolar transistor and process for fabricating same
US4648909A (en) * 1984-11-28 1987-03-10 Fairchild Semiconductor Corporation Fabrication process employing special masks for the manufacture of high speed bipolar analog integrated circuits
US4910160A (en) * 1989-06-06 1990-03-20 National Semiconductor Corporation High voltage complementary NPN/PNP process
GB2247780A (en) * 1990-09-04 1992-03-11 Samsung Electronics Co Ltd Fabricating a bipolar transistor
US5198373A (en) * 1991-05-21 1993-03-30 Sharp Kabushiki Kaisha Process for fabricating a semiconductor device

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EP0035126A2 (en) * 1980-03-03 1981-09-09 International Business Machines Corporation Bipolar transistor and process for fabricating same
US4648909A (en) * 1984-11-28 1987-03-10 Fairchild Semiconductor Corporation Fabrication process employing special masks for the manufacture of high speed bipolar analog integrated circuits
US4910160A (en) * 1989-06-06 1990-03-20 National Semiconductor Corporation High voltage complementary NPN/PNP process
GB2247780A (en) * 1990-09-04 1992-03-11 Samsung Electronics Co Ltd Fabricating a bipolar transistor
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EP0818055A1 (en) * 1995-03-27 1998-01-14 Micrel Incorporated Self-alignment technique for semiconductor devices
EP0818055A4 (en) * 1995-03-27 1998-05-06 Micrel Inc Self-alignment technique for semiconductor devices
CN104992966A (en) * 2015-05-21 2015-10-21 中国电子科技集团公司第十三研究所 Manufacturing method of bipolar high-frequency power transistor chip low in thermal budget
CN104992966B (en) * 2015-05-21 2017-10-24 中国电子科技集团公司第十三研究所 A kind of preparation method of the low bipolar high frequency power transistor chip of heat budget

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