DE3786785D1 - Verfahren zur herstellung von mos-bauelementen fuer integrierte schaltungen. - Google Patents

Verfahren zur herstellung von mos-bauelementen fuer integrierte schaltungen.

Info

Publication number
DE3786785D1
DE3786785D1 DE8787906729T DE3786785T DE3786785D1 DE 3786785 D1 DE3786785 D1 DE 3786785D1 DE 8787906729 T DE8787906729 T DE 8787906729T DE 3786785 T DE3786785 T DE 3786785T DE 3786785 D1 DE3786785 D1 DE 3786785D1
Authority
DE
Germany
Prior art keywords
integrated circuits
mos components
producing mos
producing
components
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE8787906729T
Other languages
English (en)
Other versions
DE3786785T2 (de
Inventor
Gayle Miller
Nicholas Szluk
George Maheras
Werner Metz
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SK Hynix Inc
NCR International Inc
Original Assignee
NCR International Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NCR International Inc filed Critical NCR International Inc
Application granted granted Critical
Publication of DE3786785D1 publication Critical patent/DE3786785D1/de
Publication of DE3786785T2 publication Critical patent/DE3786785T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/107—Substrate region of field-effect devices
    • H01L29/1075—Substrate region of field-effect devices of field-effect transistors
    • H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
    • H01L29/1083—Substrate region of field-effect devices of field-effect transistors with insulated gate with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
DE87906729T 1986-10-23 1987-10-05 Verfahren zur herstellung von mos-bauelementen für integrierte schaltungen. Expired - Lifetime DE3786785T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/922,221 US4682404A (en) 1986-10-23 1986-10-23 MOSFET process using implantation through silicon

Publications (2)

Publication Number Publication Date
DE3786785D1 true DE3786785D1 (de) 1993-09-02
DE3786785T2 DE3786785T2 (de) 1994-02-24

Family

ID=25446720

Family Applications (1)

Application Number Title Priority Date Filing Date
DE87906729T Expired - Lifetime DE3786785T2 (de) 1986-10-23 1987-10-05 Verfahren zur herstellung von mos-bauelementen für integrierte schaltungen.

Country Status (5)

Country Link
US (1) US4682404A (de)
EP (1) EP0289534B1 (de)
JP (1) JP2626681B2 (de)
DE (1) DE3786785T2 (de)
WO (1) WO1988003329A1 (de)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4876213A (en) * 1988-10-31 1989-10-24 Motorola, Inc. Salicided source/drain structure
US5563093A (en) * 1993-01-28 1996-10-08 Kawasaki Steel Corporation Method of manufacturing fet semiconductor devices with polysilicon gate having large grain sizes
KR0171732B1 (ko) * 1993-11-26 1999-03-30 김주용 모스 트랜지스터 및 그 제조방법
KR970003837B1 (en) * 1993-12-16 1997-03-22 Lg Semicon Co Ltd Fabrication of mosfet
KR100189964B1 (ko) * 1994-05-16 1999-06-01 윤종용 고전압 트랜지스터 및 그 제조방법
KR960042942A (ko) * 1995-05-04 1996-12-21 빈센트 비.인그라시아 반도체 디바이스 형성 방법
JPH09129848A (ja) * 1995-11-06 1997-05-16 Mitsubishi Electric Corp キャパシタを有する半導体装置の製造方法
US5923984A (en) * 1997-04-21 1999-07-13 Advanced Micro Devices, Inc. Method of making enhancement-mode and depletion-mode IGFETS with different gate materials
US5929496A (en) * 1997-12-18 1999-07-27 Gardner; Mark I. Method and structure for channel length reduction in insulated gate field effect transistors
US6207516B1 (en) * 1998-12-17 2001-03-27 United Microelectronics Corp. Method of fabricating gate oxide layer with different thickness
US6284672B1 (en) * 1999-03-02 2001-09-04 Advanced Micro Devices, Inc. Method of forming a super-shallow amorphous layer in silicon
US6429124B1 (en) * 1999-04-14 2002-08-06 Micron Technology, Inc. Local interconnect structures for integrated circuits and methods for making the same
TW410382B (en) * 1999-06-11 2000-11-01 United Microelectronics Corp Method of manufacturing forming metal oxide semiconductor transistor with raised source/drain
JP4620282B2 (ja) * 2001-04-24 2011-01-26 ルネサスエレクトロニクス株式会社 半導体装置
US6885078B2 (en) * 2001-11-09 2005-04-26 Lsi Logic Corporation Circuit isolation utilizing MeV implantation
TWI301669B (en) * 2002-09-12 2008-10-01 Au Optronics Corp Method of forming lightly doped drains
JP2004221246A (ja) * 2003-01-14 2004-08-05 Seiko Epson Corp 半導体装置及びその製造方法
JP4725451B2 (ja) * 2006-03-27 2011-07-13 ヤマハ株式会社 絶縁ゲート型電界効果トランジスタの製法
US9478467B2 (en) 2014-11-17 2016-10-25 Freescale Semiconductor, Inc. Semiconductor device including power and logic devices and related fabrication methods
US11152381B1 (en) * 2020-04-13 2021-10-19 HeFeChip Corporation Limited MOS transistor having lower gate-to-source/drain breakdown voltage and one-time programmable memory device using the same
US11114140B1 (en) 2020-04-23 2021-09-07 HeFeChip Corporation Limited One time programmable (OTP) bits for physically unclonable functions
US11437082B2 (en) 2020-05-17 2022-09-06 HeFeChip Corporation Limited Physically unclonable function circuit having lower gate-to-source/drain breakdown voltage

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4069067A (en) * 1975-03-20 1978-01-17 Matsushita Electric Industrial Co., Ltd. Method of making a semiconductor device
JPS6041470B2 (ja) * 1976-06-15 1985-09-17 松下電器産業株式会社 半導体装置の製造方法
DE2739662A1 (de) * 1977-09-02 1979-03-08 Siemens Ag Verfahren zur herstellung von mos-transistoren
US4182023A (en) * 1977-10-21 1980-01-08 Ncr Corporation Process for minimum overlap silicon gate devices
US4149904A (en) * 1977-10-21 1979-04-17 Ncr Corporation Method for forming ion-implanted self-aligned gate structure by controlled ion scattering
JPS54140483A (en) * 1978-04-21 1979-10-31 Nec Corp Semiconductor device
US4198250A (en) * 1979-02-05 1980-04-15 Intel Corporation Shadow masking process for forming source and drain regions for field-effect transistors and like regions
US4452645A (en) * 1979-11-13 1984-06-05 International Business Machines Corporation Method of making emitter regions by implantation through a non-monocrystalline layer
US4317273A (en) * 1979-11-13 1982-03-02 Texas Instruments Incorporated Method of making high coupling ratio DMOS electrically programmable ROM
JPS56162873A (en) * 1980-05-19 1981-12-15 Nec Corp Insulated gate type field effect semiconductor device
JPS5756973A (en) * 1980-09-20 1982-04-05 Mitsubishi Electric Corp Manufacture of insulated gate type field effect transistor
US4330931A (en) * 1981-02-03 1982-05-25 Intel Corporation Process for forming metal plated regions and lines in MOS circuits
EP0083447B1 (de) * 1981-12-30 1989-04-26 Thomson Components-Mostek Corporation Dreifach diffundierte Anordnung mit kurzem Kanal
US4599118A (en) * 1981-12-30 1986-07-08 Mostek Corporation Method of making MOSFET by multiple implantations followed by a diffusion step
US4536944A (en) * 1982-12-29 1985-08-27 International Business Machines Corporation Method of making ROM/PLA semiconductor device by late stage personalization
JPS59220971A (ja) * 1983-05-31 1984-12-12 Toshiba Corp 半導体装置の製造方法
JPS6063961A (ja) * 1983-08-30 1985-04-12 Fujitsu Ltd 半導体装置の製造方法
JPS60245281A (ja) * 1984-05-21 1985-12-05 Matsushita Electronics Corp 半導体装置の製造方法

Also Published As

Publication number Publication date
DE3786785T2 (de) 1994-02-24
JP2626681B2 (ja) 1997-07-02
JPH01501189A (ja) 1989-04-20
WO1988003329A1 (en) 1988-05-05
EP0289534A1 (de) 1988-11-09
US4682404A (en) 1987-07-28
EP0289534B1 (de) 1993-07-28

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: AT&T GLOBAL INFORMATION SOLUTIONS INTERNATIONAL IN

8327 Change in the person/name/address of the patent owner

Owner name: AT&T GLOBAL INFORMATION SOLUTIONS INTERNATIONAL IN

8327 Change in the person/name/address of the patent owner

Owner name: NCR INTERNATIONAL, INC. (N.D.GES.D.STAATES DELAWAR

8327 Change in the person/name/address of the patent owner

Owner name: NCR INTERNATIONAL, INC. (N.D.GES.D.STAATES DELAWAR

8328 Change in the person/name/address of the agent

Free format text: V. BEZOLD & SOZIEN, 80799 MUENCHEN

8327 Change in the person/name/address of the patent owner

Owner name: HYNIX SEMICONDUCTOR INC., ICHON, KYONGGI, KR

Owner name: NCR INTERNATIONAL, INC. (N.D.GES.D.STAATES DEL, US