DE3765718D1 - Verfahren zur herstellung von cmos-strukturen. - Google Patents
Verfahren zur herstellung von cmos-strukturen.Info
- Publication number
- DE3765718D1 DE3765718D1 DE8787901177T DE3765718T DE3765718D1 DE 3765718 D1 DE3765718 D1 DE 3765718D1 DE 8787901177 T DE8787901177 T DE 8787901177T DE 3765718 T DE3765718 T DE 3765718T DE 3765718 D1 DE3765718 D1 DE 3765718D1
- Authority
- DE
- Germany
- Prior art keywords
- cmos structures
- producing cmos
- producing
- structures
- cmos
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000004519 manufacturing process Methods 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823864—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US06/822,075 US4703551A (en) | 1986-01-24 | 1986-01-24 | Process for forming LDD MOS/CMOS structures |
PCT/US1987/000082 WO1987004564A1 (en) | 1986-01-24 | 1987-01-20 | Process for forming cmos structures |
Publications (1)
Publication Number | Publication Date |
---|---|
DE3765718D1 true DE3765718D1 (de) | 1990-11-29 |
Family
ID=25235058
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE198787901177T Pending DE256085T1 (de) | 1986-01-24 | 1987-01-20 | Verfahren zur herstellung von cmos-strukturen. |
DE8787901177T Expired - Lifetime DE3765718D1 (de) | 1986-01-24 | 1987-01-20 | Verfahren zur herstellung von cmos-strukturen. |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE198787901177T Pending DE256085T1 (de) | 1986-01-24 | 1987-01-20 | Verfahren zur herstellung von cmos-strukturen. |
Country Status (6)
Country | Link |
---|---|
US (1) | US4703551A (de) |
EP (1) | EP0256085B1 (de) |
JP (1) | JP2662230B2 (de) |
CA (1) | CA1256588A (de) |
DE (2) | DE256085T1 (de) |
WO (1) | WO1987004564A1 (de) |
Families Citing this family (40)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0187016B1 (de) * | 1984-12-27 | 1991-02-20 | Kabushiki Kaisha Toshiba | MISFET mit niedrigdotiertem Drain und Verfahren zu seiner Herstellung |
US4760033A (en) * | 1986-04-08 | 1988-07-26 | Siemens Aktiengesellschaft | Method for the manufacture of complementary MOS field effect transistors in VLSI technology |
US4786609A (en) * | 1987-10-05 | 1988-11-22 | North American Philips Corporation, Signetics Division | Method of fabricating field-effect transistor utilizing improved gate sidewall spacers |
US5183777A (en) * | 1987-12-30 | 1993-02-02 | Fujitsu Limited | Method of forming shallow junctions |
US4855247A (en) * | 1988-01-19 | 1989-08-08 | Standard Microsystems Corporation | Process for fabricating self-aligned silicide lightly doped drain MOS devices |
NL8800222A (nl) * | 1988-01-29 | 1989-08-16 | Philips Nv | Werkwijze voor het vervaardigen van een halfgeleiderinrichting waarbij op zelfregistrerende wijze metaalsilicide wordt aangebracht. |
US4923824A (en) * | 1988-04-27 | 1990-05-08 | Vtc Incorporated | Simplified method of fabricating lightly doped drain insulated gate field effect transistors |
US4943537A (en) * | 1988-06-23 | 1990-07-24 | Dallas Semiconductor Corporation | CMOS integrated circuit with reduced susceptibility to PMOS punchthrough |
JPH0666329B2 (ja) * | 1988-06-30 | 1994-08-24 | 株式会社東芝 | 半導体装置の製造方法 |
US5273914A (en) * | 1988-10-14 | 1993-12-28 | Matsushita Electric Industrial Co., Ltd. | Method of fabricating a CMOS semiconductor devices |
US5030582A (en) * | 1988-10-14 | 1991-07-09 | Matsushita Electric Industrial Co., Ltd. | Method of fabricating a CMOS semiconductor device |
US4874713A (en) * | 1989-05-01 | 1989-10-17 | Ncr Corporation | Method of making asymmetrically optimized CMOS field effect transistors |
JPH0777263B2 (ja) * | 1989-06-13 | 1995-08-16 | シャープ株式会社 | 半導体装置の製造方法 |
US5153145A (en) * | 1989-10-17 | 1992-10-06 | At&T Bell Laboratories | Fet with gate spacer |
US5296401A (en) * | 1990-01-11 | 1994-03-22 | Mitsubishi Denki Kabushiki Kaisha | MIS device having p channel MOS device and n channel MOS device with LDD structure and manufacturing method thereof |
US5266510A (en) * | 1990-08-09 | 1993-11-30 | Micron Technology, Inc. | High performance sub-micron p-channel transistor with germanium implant |
US5185280A (en) * | 1991-01-29 | 1993-02-09 | Texas Instruments Incorporated | Method of fabricating a soi transistor with pocket implant and body-to-source (bts) contact |
JP2717237B2 (ja) | 1991-05-16 | 1998-02-18 | 株式会社 半導体エネルギー研究所 | 絶縁ゲイト型半導体装置およびその作製方法 |
US5439831A (en) * | 1994-03-09 | 1995-08-08 | Siemens Aktiengesellschaft | Low junction leakage MOSFETs |
US5536959A (en) * | 1994-09-09 | 1996-07-16 | Mcnc | Self-aligned charge screen (SACS) field effect transistors and methods |
JP3521097B2 (ja) * | 1995-07-03 | 2004-04-19 | シャープ株式会社 | 表面チャネル型cmosトランジスタの製造方法 |
US6787844B2 (en) * | 1995-09-29 | 2004-09-07 | Nippon Steel Corporation | Semiconductor device including transistor with composite gate structure and transistor with single gate structure, and method for manufacturing the same |
US6720627B1 (en) * | 1995-10-04 | 2004-04-13 | Sharp Kabushiki Kaisha | Semiconductor device having junction depths for reducing short channel effect |
US6346439B1 (en) | 1996-07-09 | 2002-02-12 | Micron Technology, Inc. | Semiconductor transistor devices and methods for forming semiconductor transistor devices |
US5817564A (en) * | 1996-06-28 | 1998-10-06 | Harris Corporation | Double diffused MOS device and method |
KR100253372B1 (ko) * | 1997-12-08 | 2000-04-15 | 김영환 | 반도체 소자 및 그 제조방법 |
US5956584A (en) * | 1998-03-30 | 1999-09-21 | Texas Instruments - Acer Incorporated | Method of making self-aligned silicide CMOS transistors |
US6051458A (en) * | 1998-05-04 | 2000-04-18 | Taiwan Semiconductor Manufacturing Company | Drain and source engineering for ESD-protection transistors |
US6274448B1 (en) * | 1998-12-08 | 2001-08-14 | United Microelectronics Corp. | Method of suppressing junction capacitance of source/drain regions |
EP1011137A1 (de) * | 1998-12-16 | 2000-06-21 | STMicroelectronics S.r.l. | Verfahren zum Integrieren von Widerständen und ESD-Selbstschutz-Transistoren mit Speichermatrix |
JP2001168323A (ja) * | 1999-12-06 | 2001-06-22 | Mitsubishi Electric Corp | 半導体装置の製造方法 |
US6445050B1 (en) * | 2000-02-08 | 2002-09-03 | International Business Machines Corporation | Symmetric device with contacts self aligned to gate |
US6780700B2 (en) * | 2000-08-28 | 2004-08-24 | Sharp Laboratories Of America, Inc. | Method of fabricating deep sub-micron CMOS source/drain with MDD and selective CVD silicide |
US6534781B2 (en) * | 2000-12-26 | 2003-03-18 | Ovonyx, Inc. | Phase-change memory bipolar array utilizing a single shallow trench isolation for creating an individual active area region for two memory array elements and one bipolar base contact |
JP4615755B2 (ja) * | 2001-04-04 | 2011-01-19 | セイコーインスツル株式会社 | 半導体装置の製造方法 |
US6808974B2 (en) | 2001-05-15 | 2004-10-26 | International Business Machines Corporation | CMOS structure with maximized polysilicon gate activation and a method for selectively maximizing doping activation in gate, extension, and source/drain regions |
DE10126800B4 (de) * | 2001-06-01 | 2010-07-01 | Infineon Technologies Ag | Verfahren und Vorrichtung zum Testen der ESD-Festigkeit eines Halbleiter-Bauelements |
US20040238896A1 (en) * | 2003-06-02 | 2004-12-02 | Marie Mochizuki | Semiconductor device |
KR102160100B1 (ko) | 2014-05-27 | 2020-09-25 | 삼성전자 주식회사 | 반도체 장치 제조 방법 |
US9558950B1 (en) * | 2015-08-19 | 2017-01-31 | International Business Machines Corporation | Overhang hardmask to prevent parasitic epitaxial nodules at gate end during source drain epitaxy |
Family Cites Families (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4198250A (en) * | 1979-02-05 | 1980-04-15 | Intel Corporation | Shadow masking process for forming source and drain regions for field-effect transistors and like regions |
JPS5621370A (en) * | 1979-07-31 | 1981-02-27 | Chiyou Lsi Gijutsu Kenkyu Kumiai | Mos transistor |
US4356623A (en) * | 1980-09-15 | 1982-11-02 | Texas Instruments Incorporated | Fabrication of submicron semiconductor devices |
JPS5766674A (en) * | 1980-10-09 | 1982-04-22 | Toshiba Corp | Semiconductor device |
US4366613A (en) * | 1980-12-17 | 1983-01-04 | Ibm Corporation | Method of fabricating an MOS dynamic RAM with lightly doped drain |
US4599118A (en) * | 1981-12-30 | 1986-07-08 | Mostek Corporation | Method of making MOSFET by multiple implantations followed by a diffusion step |
US4590663A (en) * | 1982-02-01 | 1986-05-27 | Texas Instruments Incorporated | High voltage CMOS technology with N-channel source/drain extensions |
JPS58175846A (ja) * | 1982-04-08 | 1983-10-15 | Toshiba Corp | 半導体装置の製造方法 |
US4536944A (en) * | 1982-12-29 | 1985-08-27 | International Business Machines Corporation | Method of making ROM/PLA semiconductor device by late stage personalization |
JPS59188974A (ja) * | 1983-04-11 | 1984-10-26 | Nec Corp | 半導体装置の製造方法 |
US4503601A (en) * | 1983-04-18 | 1985-03-12 | Ncr Corporation | Oxide trench structure for polysilicon gates and interconnects |
JPS6072272A (ja) * | 1983-09-28 | 1985-04-24 | Toshiba Corp | 半導体装置の製造方法 |
US4597824A (en) * | 1983-11-11 | 1986-07-01 | Kabushiki Kaisha Toshiba | Method of producing semiconductor device |
FR2555365B1 (fr) * | 1983-11-22 | 1986-08-29 | Efcis | Procede de fabrication de circuit integre avec connexions de siliciure de tantale et circuit integre realise selon ce procede |
US4519126A (en) * | 1983-12-12 | 1985-05-28 | Rca Corporation | Method of fabricating high speed CMOS devices |
JPS60134473A (ja) * | 1983-12-22 | 1985-07-17 | Seiko Epson Corp | 半導体装置製造方法 |
US4512073A (en) * | 1984-02-23 | 1985-04-23 | Rca Corporation | Method of forming self-aligned contact openings |
JPS60193371A (ja) * | 1984-03-15 | 1985-10-01 | Toshiba Corp | 半導体装置の製造方法 |
US4578128A (en) * | 1984-12-03 | 1986-03-25 | Ncr Corporation | Process for forming retrograde dopant distributions utilizing simultaneous outdiffusion of dopants |
US4621413A (en) * | 1985-06-03 | 1986-11-11 | Motorola, Inc. | Fabricating a semiconductor device with reduced gate leakage |
JPS61295652A (ja) * | 1985-06-25 | 1986-12-26 | Oki Electric Ind Co Ltd | Cmos型半導体装置の製造方法 |
JPH105277A (ja) * | 1996-06-26 | 1998-01-13 | Kao Corp | 使い捨ておむつ |
-
1986
- 1986-01-24 US US06/822,075 patent/US4703551A/en not_active Expired - Lifetime
-
1987
- 1987-01-06 CA CA000526713A patent/CA1256588A/en not_active Expired
- 1987-01-20 EP EP87901177A patent/EP0256085B1/de not_active Expired - Lifetime
- 1987-01-20 DE DE198787901177T patent/DE256085T1/de active Pending
- 1987-01-20 WO PCT/US1987/000082 patent/WO1987004564A1/en active IP Right Grant
- 1987-01-20 DE DE8787901177T patent/DE3765718D1/de not_active Expired - Lifetime
- 1987-01-20 JP JP62501145A patent/JP2662230B2/ja not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JPS63503025A (ja) | 1988-11-02 |
JP2662230B2 (ja) | 1997-10-08 |
EP0256085B1 (de) | 1990-10-24 |
WO1987004564A1 (en) | 1987-07-30 |
EP0256085A1 (de) | 1988-02-24 |
US4703551A (en) | 1987-11-03 |
CA1256588A (en) | 1989-06-27 |
DE256085T1 (de) | 1988-09-01 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
DE3765718D1 (de) | Verfahren zur herstellung von cmos-strukturen. | |
DE3761744D1 (de) | Verfahren zur herstellung von granulaten. | |
DE3881799D1 (de) | Verfahren zur herstellung von cmos-bauelementen. | |
DE3772818D1 (de) | Verfahren zur herstellung von reinigungsmittelpulver. | |
DE3762745D1 (de) | Verfahren zur herstellung von 2-chlor-5-chlormethylthiazol. | |
DE3763558D1 (de) | Verfahren zur herstellung von 2-chlor-5-chlormethylpyridin. | |
DE3784151D1 (de) | Verfahren zur herstellung von alkylhalosilanen. | |
DE3773889D1 (de) | Verfahren zur herstellung von merkaptomethylphenolen. | |
DE3853160D1 (de) | Verfahren zur herstellung von elektrophotographien. | |
DE3865476D1 (de) | Verfahren zur herstellung von aminopropylalkoxysilanen. | |
DE3780704D1 (de) | Verfahren zur herstellung von n-acyltetrahydroisochinoline. | |
DE3860666D1 (de) | Verfahren zur herstellung von hexabromcyclododekan. | |
DE3771806D1 (de) | Verfahren zur herstellung von 3-halogen-2-hydroxypropyl-trimethylammonium-halogenid. | |
DE3861891D1 (de) | Verfahren zur herstellung von epichlorhydrinen. | |
DE3863586D1 (de) | Verfahren zur herstellung von m-triflourmethylphenylacetonitril. | |
DE3768424D1 (de) | Verfahren zur herstellung von halogenierten polyaethern. | |
DE3765129D1 (de) | Verfahren zur herstellung von nitrilen. | |
DE3769076D1 (de) | Verfahren zur herstellung von fluorbenzaldehyden. | |
DE3766910D1 (de) | Verfahren zur herstellung von dihydrocyclocitral. | |
ATE49919T1 (de) | Verfahren zur herstellung von verbundteilen. | |
DE3863321D1 (de) | Verfahren zur herstellung von naphthacenen. | |
DE3777475D1 (de) | Verfahren zur herstellung von polyphenylen-ether-polyester-copolymeren. | |
DE3769263D1 (de) | Verfahren zur herstellung von bromfluoroethylhypofluorit. | |
DE3776980D1 (de) | Verfahren zur herstellung von feinstrukturen. | |
DE3781699D1 (de) | Verfahren zur herstellung von l-sorbose. |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8327 | Change in the person/name/address of the patent owner |
Owner name: SAMSUNG ELECTRONICS CO., LTD., SEOUL, KR |
|
8328 | Change in the person/name/address of the agent |
Representative=s name: FIENER, J., PAT.-ANW., 87719 MINDELHEIM |