DE69220559D1 - Verfahren zur Herstellung von Kontakten in Löchern in integrierten Schaltungen - Google Patents
Verfahren zur Herstellung von Kontakten in Löchern in integrierten SchaltungenInfo
- Publication number
- DE69220559D1 DE69220559D1 DE69220559T DE69220559T DE69220559D1 DE 69220559 D1 DE69220559 D1 DE 69220559D1 DE 69220559 T DE69220559 T DE 69220559T DE 69220559 T DE69220559 T DE 69220559T DE 69220559 D1 DE69220559 D1 DE 69220559D1
- Authority
- DE
- Germany
- Prior art keywords
- holes
- integrated circuits
- making contacts
- contacts
- making
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US80993791A | 1991-12-18 | 1991-12-18 |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69220559D1 true DE69220559D1 (de) | 1997-07-31 |
DE69220559T2 DE69220559T2 (de) | 1997-12-18 |
Family
ID=25202544
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69220559T Expired - Fee Related DE69220559T2 (de) | 1991-12-18 | 1992-12-17 | Verfahren zur Herstellung von Kontakten in Löchern in integrierten Schaltungen |
Country Status (4)
Country | Link |
---|---|
US (2) | US5423939A (de) |
EP (1) | EP0547906B1 (de) |
JP (1) | JPH05267209A (de) |
DE (1) | DE69220559T2 (de) |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5693564A (en) * | 1994-12-22 | 1997-12-02 | Intel Corporation | Conductor fill reflow with intermetallic compound wetting layer for semiconductor fabrication |
US5804251A (en) * | 1995-12-29 | 1998-09-08 | Intel Corporation | Low temperature aluminum alloy plug technology |
US5789317A (en) | 1996-04-12 | 1998-08-04 | Micron Technology, Inc. | Low temperature reflow method for filling high aspect ratio contacts |
US5985746A (en) * | 1996-11-21 | 1999-11-16 | Lsi Logic Corporation | Process for forming self-aligned conductive plugs in multiple insulation levels in integrated circuit structures and resulting product |
US5951824A (en) * | 1997-06-19 | 1999-09-14 | Beloit Technologies, Inc. | Compliant hydrodynamic/hydrostatic shoe for papermaking press |
US6365514B1 (en) | 1997-12-23 | 2002-04-02 | Intel Corporation | Two chamber metal reflow process |
TW407342B (en) * | 1998-06-17 | 2000-10-01 | United Microelectronics Corp | Planarization method of damascene structure |
US6047637A (en) * | 1999-06-17 | 2000-04-11 | Fujitsu Limited | Method of paste printing using stencil and masking layer |
US6114243A (en) * | 1999-11-15 | 2000-09-05 | Chartered Semiconductor Manufacturing Ltd | Method to avoid copper contamination on the sidewall of a via or a dual damascene structure |
KR100400037B1 (ko) * | 2001-02-22 | 2003-09-29 | 삼성전자주식회사 | 콘택 플러그를 구비하는 반도체 소자 및 그의 제조 방법 |
US8575753B2 (en) * | 2009-05-27 | 2013-11-05 | Samsung Electronics Co., Ltd. | Semiconductor device having a conductive structure including oxide and non oxide portions |
US20120168210A1 (en) * | 2011-01-05 | 2012-07-05 | International Business Machines Corporation | Methods and Structures Involving Terminal Connections |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4174562A (en) * | 1973-11-02 | 1979-11-20 | Harris Corporation | Process for forming metallic ground grid for integrated circuits |
US4185294A (en) * | 1975-12-10 | 1980-01-22 | Tokyo Shibaura Electric Co., Ltd. | Semiconductor device and a method for manufacturing the same |
US4478679A (en) * | 1983-11-30 | 1984-10-23 | Storage Technology Partners | Self-aligning process for placing a barrier metal over the source and drain regions of MOS semiconductors |
US4575402A (en) * | 1985-02-13 | 1986-03-11 | Hewlett-Packard Company | Method for fabricating conductors in integrated circuits |
US4789648A (en) * | 1985-10-28 | 1988-12-06 | International Business Machines Corporation | Method for producing coplanar multi-level metal/insulator films on a substrate and for forming patterned conductive lines simultaneously with stud vias |
US4689113A (en) * | 1986-03-21 | 1987-08-25 | International Business Machines Corporation | Process for forming planar chip-level wiring |
US4832787A (en) * | 1988-02-19 | 1989-05-23 | International Business Machines Corporation | Gas mixture and method for anisotropic selective etch of nitride |
US4832789A (en) * | 1988-04-08 | 1989-05-23 | American Telephone And Telegrph Company, At&T Bell Laboratories | Semiconductor devices having multi-level metal interconnects |
US4822753A (en) * | 1988-05-09 | 1989-04-18 | Motorola, Inc. | Method for making a w/tin contact |
US5008216A (en) * | 1988-10-03 | 1991-04-16 | International Business Machines Corporation | Process for improved contact stud structure for semiconductor devices |
US4961822A (en) * | 1989-04-17 | 1990-10-09 | Liao Kuan Y | Fully recessed interconnection scheme with titanium-tungsten and selective CVD tungsten |
DE69031357T2 (de) * | 1989-04-21 | 1998-04-02 | Nippon Electric Co | Halbleiteranordnung mit Mehrschichtleiter |
US4933303A (en) * | 1989-07-25 | 1990-06-12 | Standard Microsystems Corporation | Method of making self-aligned tungsten interconnection in an integrated circuit |
-
1992
- 1992-12-17 DE DE69220559T patent/DE69220559T2/de not_active Expired - Fee Related
- 1992-12-17 EP EP92311557A patent/EP0547906B1/de not_active Expired - Lifetime
- 1992-12-18 JP JP4338474A patent/JPH05267209A/ja active Pending
-
1993
- 1993-08-23 US US08/110,486 patent/US5423939A/en not_active Expired - Lifetime
-
1995
- 1995-03-03 US US08/398,110 patent/US5751064A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JPH05267209A (ja) | 1993-10-15 |
US5423939A (en) | 1995-06-13 |
DE69220559T2 (de) | 1997-12-18 |
EP0547906B1 (de) | 1997-06-25 |
EP0547906A1 (de) | 1993-06-23 |
US5751064A (en) | 1998-05-12 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |