DE69120198D1 - Mehrschichtige, gedruckte Leiterplatte und Verfahren zu ihrer Herstellung - Google Patents

Mehrschichtige, gedruckte Leiterplatte und Verfahren zu ihrer Herstellung

Info

Publication number
DE69120198D1
DE69120198D1 DE69120198T DE69120198T DE69120198D1 DE 69120198 D1 DE69120198 D1 DE 69120198D1 DE 69120198 T DE69120198 T DE 69120198T DE 69120198 T DE69120198 T DE 69120198T DE 69120198 D1 DE69120198 D1 DE 69120198D1
Authority
DE
Germany
Prior art keywords
manufacture
circuit board
printed circuit
layer printed
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69120198T
Other languages
English (en)
Other versions
DE69120198T2 (de
Inventor
Hisashi Ishida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Circuit Solutions Inc
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Publication of DE69120198D1 publication Critical patent/DE69120198D1/de
Application granted granted Critical
Publication of DE69120198T2 publication Critical patent/DE69120198T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4626—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials
    • H05K3/4629—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials laminating inorganic sheets comprising printed circuits, e.g. green ceramic sheets
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4614—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0137—Materials
    • H05K2201/0154—Polyimide
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/11—Treatments characterised by their effect, e.g. heating, cooling, roughening
    • H05K2203/1189—Pressing leads, bumps or a die through an insulating layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/15—Position of the PCB during processing
    • H05K2203/1572—Processing both sides of a PCB by the same process; Providing a similar arrangement of components on both sides; Making interlayer connections from two sides
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/28—Applying non-metallic protective coatings
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
    • H05K3/4605—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated made from inorganic insulating material
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4623—Manufacturing multilayer circuits by laminating two or more circuit boards the circuit boards having internal via connections between two or more circuit layers before lamination, e.g. double-sided circuit boards
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4647—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits by applying an insulating layer around previously made via studs
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49126—Assembling bases
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
DE69120198T 1990-10-17 1991-10-16 Mehrschichtige, gedruckte Leiterplatte und Verfahren zu ihrer Herstellung Expired - Fee Related DE69120198T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2278110A JP2551224B2 (ja) 1990-10-17 1990-10-17 多層配線基板および多層配線基板の製造方法

Publications (2)

Publication Number Publication Date
DE69120198D1 true DE69120198D1 (de) 1996-07-18
DE69120198T2 DE69120198T2 (de) 1996-10-10

Family

ID=17592766

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69120198T Expired - Fee Related DE69120198T2 (de) 1990-10-17 1991-10-16 Mehrschichtige, gedruckte Leiterplatte und Verfahren zu ihrer Herstellung

Country Status (5)

Country Link
US (2) US5382757A (de)
EP (1) EP0481472B1 (de)
JP (1) JP2551224B2 (de)
CA (1) CA2053448C (de)
DE (1) DE69120198T2 (de)

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* Cited by examiner, † Cited by third party
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CA2074648C (en) * 1991-07-26 1999-02-23 Hisashi Ishida Polyimide multilayer wiring substrate and method for manufacturing the same
US5165984A (en) * 1991-07-30 1992-11-24 At&T Bell Laboratories Stepped multilayer interconnection apparatus and method of making the same
US5376226A (en) * 1993-01-28 1994-12-27 Trw Inc. Method of making connector for integrated circuit chips
JPH0828580B2 (ja) * 1993-04-21 1996-03-21 日本電気株式会社 配線基板構造及びその製造方法
DE69528868T2 (de) * 1994-08-19 2003-03-27 Hitachi Ltd Keramikzusammensetzung für Schaltungssubstrat und seine Herstellung
US5739476A (en) * 1994-10-05 1998-04-14 Namgung; Chung Multilayer printed circuit board laminated with unreinforced resin
US5487218A (en) * 1994-11-21 1996-01-30 International Business Machines Corporation Method for making printed circuit boards with selectivity filled plated through holes
JPH08181443A (ja) * 1994-12-21 1996-07-12 Murata Mfg Co Ltd セラミック多層基板およびその製造方法
JP2748890B2 (ja) * 1995-06-14 1998-05-13 日本電気株式会社 有機樹脂多層配線基板およびその製造方法
JP2917867B2 (ja) * 1995-08-14 1999-07-12 日本電気株式会社 多層配線基板
WO1997027490A1 (en) * 1996-01-25 1997-07-31 General Dynamics Information Systems, Inc. Performing an operation on an integrated circuit
JPH1027971A (ja) * 1996-07-10 1998-01-27 Nec Corp 有機薄膜多層配線基板の切断方法
AU5238898A (en) * 1996-11-08 1998-05-29 W.L. Gore & Associates, Inc. Method for reducing via inductance in an electronic assembly and device
US5858254A (en) * 1997-01-28 1999-01-12 International Business Machines Corporation Multilayered circuitized substrate and method of fabrication
US6016005A (en) * 1998-02-09 2000-01-18 Cellarosi; Mario J. Multilayer, high density micro circuit module and method of manufacturing same
US6081026A (en) * 1998-11-13 2000-06-27 Fujitsu Limited High density signal interposer with power and ground wrap
US6239485B1 (en) * 1998-11-13 2001-05-29 Fujitsu Limited Reduced cross-talk noise high density signal interposer with power and ground wrap
JP3629375B2 (ja) * 1998-11-27 2005-03-16 新光電気工業株式会社 多層回路基板の製造方法
JP3635219B2 (ja) * 1999-03-11 2005-04-06 新光電気工業株式会社 半導体装置用多層基板及びその製造方法
US6353997B1 (en) * 1999-10-07 2002-03-12 Subtron Technology Co., Ltd. Layer build-up method for manufacturing multi-layer board
US6882045B2 (en) * 1999-10-28 2005-04-19 Thomas J. Massingill Multi-chip module and method for forming and method for deplating defective capacitors
US6428942B1 (en) 1999-10-28 2002-08-06 Fujitsu Limited Multilayer circuit structure build up method
US6869750B2 (en) * 1999-10-28 2005-03-22 Fujitsu Limited Structure and method for forming a multilayered structure
JP2001217508A (ja) * 2000-01-31 2001-08-10 Toshiba Corp プリント基板
US6734369B1 (en) * 2000-08-31 2004-05-11 International Business Machines Corporation Surface laminar circuit board having pad disposed within a through hole
US6568250B1 (en) * 2000-09-22 2003-05-27 International Business Machines Corporation Apparatus and method for determining residual stress
JP2002368422A (ja) * 2001-04-04 2002-12-20 Murata Mfg Co Ltd 多層セラミック基板及びその製造方法
US6810583B2 (en) 2001-08-07 2004-11-02 International Business Machines Corporation Coupling of conductive vias to complex power-signal substructures
TW573444B (en) * 2003-04-22 2004-01-21 Ind Tech Res Inst Substrate having organic and inorganic functional package
US20050029011A1 (en) * 2003-08-07 2005-02-10 Matsushita Electric Industrial Co., Ltd. Circuit board
JP4073945B1 (ja) * 2007-01-12 2008-04-09 新光電気工業株式会社 多層配線基板の製造方法
JP2009170753A (ja) * 2008-01-18 2009-07-30 Panasonic Corp 多層プリント配線板とこれを用いた実装体
JP5550280B2 (ja) 2009-07-29 2014-07-16 京セラ株式会社 多層配線基板
TW201110839A (en) 2009-09-04 2011-03-16 Advanced Semiconductor Eng Substrate structure and method for manufacturing the same
KR20110113980A (ko) * 2010-04-12 2011-10-19 삼성전자주식회사 필름을 포함한 다층 인쇄회로기판 및 그 제조 방법
US20190045620A1 (en) * 2014-07-09 2019-02-07 Schreiner Group Gmbh & Co. Kg Sensor device with a flexible electrical conductor structure
TWI558277B (zh) * 2014-08-19 2016-11-11 乾坤科技股份有限公司 電路板層間導電結構、磁性元件及其製作方法
WO2019098012A1 (ja) * 2017-11-16 2019-05-23 株式会社村田製作所 樹脂多層基板、電子部品およびその実装構造
KR102537710B1 (ko) * 2021-05-28 2023-05-31 (주)티에스이 일괄 접합 방식의 다층 회로기판 및 그 제조 방법

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JPS55133597A (en) * 1979-04-06 1980-10-17 Hitachi Ltd Multilayer circuit board
FR2476913B1 (fr) * 1980-02-25 1985-09-13 Nippon Electric Co Circuit a plusieurs couches pour integration a grande echelle et procede de fabrication de ce circuit
US4522667A (en) * 1980-06-25 1985-06-11 General Electric Company Method for making multi-layer metal core circuit board laminate with a controlled thermal coefficient of expansion
JPS6014494A (ja) * 1983-07-04 1985-01-25 株式会社日立製作所 セラミツク多層配線基板およびその製造方法
FR2567684B1 (fr) * 1984-07-10 1988-11-04 Nec Corp Module ayant un substrat ceramique multicouche et un circuit multicouche sur ce substrat et procede pour sa fabrication
US4541035A (en) * 1984-07-30 1985-09-10 General Electric Company Low loss, multilevel silicon circuit board
JPH0716094B2 (ja) * 1986-03-31 1995-02-22 日立化成工業株式会社 配線板の製造法
JPS6366993A (ja) * 1986-09-08 1988-03-25 日本電気株式会社 多層配線基板
US4740414A (en) * 1986-11-17 1988-04-26 Rockwell International Corporation Ceramic/organic multilayer interconnection board
DE3639402A1 (de) * 1986-11-18 1988-05-19 Siemens Ag Verfahren zur herstellung einer mehrschichtigen leiterplatte sowie danach hergestellte leiterplatte
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JPH0268992A (ja) * 1988-09-02 1990-03-08 Nec Corp 多層配線基板

Also Published As

Publication number Publication date
JP2551224B2 (ja) 1996-11-06
US5337466A (en) 1994-08-16
JPH04152693A (ja) 1992-05-26
US5382757A (en) 1995-01-17
EP0481472A1 (de) 1992-04-22
EP0481472B1 (de) 1996-06-12
CA2053448C (en) 1996-09-17
CA2053448A1 (en) 1992-04-18
DE69120198T2 (de) 1996-10-10

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: NEC TOPPAN CIRCUIT SOLUTIONS,INC., TOKIO/TOKYO, JP

8339 Ceased/non-payment of the annual fee