DE69115619D1 - Leiterplatte und Verfahren zu ihrer Herstellung - Google Patents

Leiterplatte und Verfahren zu ihrer Herstellung

Info

Publication number
DE69115619D1
DE69115619D1 DE69115619T DE69115619T DE69115619D1 DE 69115619 D1 DE69115619 D1 DE 69115619D1 DE 69115619 T DE69115619 T DE 69115619T DE 69115619 T DE69115619 T DE 69115619T DE 69115619 D1 DE69115619 D1 DE 69115619D1
Authority
DE
Germany
Prior art keywords
manufacture
circuit board
printed circuit
printed
board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69115619T
Other languages
English (en)
Other versions
DE69115619T2 (de
Inventor
Eiji Horikoshi
Motoaki Tani
Isao Watanabe
Katsuhide Natori
Takehiro Sato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of DE69115619D1 publication Critical patent/DE69115619D1/de
Application granted granted Critical
Publication of DE69115619T2 publication Critical patent/DE69115619T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/05—Insulated conductive substrates, e.g. insulated metal substrate
    • H05K1/056—Insulated conductive substrates, e.g. insulated metal substrate the metal substrate being covered by an organic insulating layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/44—Manufacturing insulated metal core circuits or other insulated electrically conductive core circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0137—Materials
    • H05K2201/0166—Polymeric layer used for special processing, e.g. resist for etching insulating material or photoresist used as a mask during plasma etching
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09509—Blind vias, i.e. vias having one side closed
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09554—Via connected to metal substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/13—Moulding and encapsulation; Deposition techniques; Protective layers
    • H05K2203/1333—Deposition techniques, e.g. coating
    • H05K2203/135—Electrophoretic deposition of insulating material
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0017—Etching of the substrate by chemical or physical means
    • H05K3/0023—Etching of the substrate by chemical or physical means by exposure and development of a photosensitive insulating layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0017—Etching of the substrate by chemical or physical means
    • H05K3/0041—Etching of the substrate by chemical or physical means by plasma etching
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/44—Manufacturing insulated metal core circuits or other insulated electrically conductive core circuits
    • H05K3/445—Manufacturing insulated metal core circuits or other insulated electrically conductive core circuits having insulated holes or insulated via connections through the metal core
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
    • H05K3/4608—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated comprising an electrically conductive base or core
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/24—Structurally defined web or sheet [e.g., overall dimension, etc.]
    • Y10T428/24802—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.]
    • Y10T428/24917—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.] including metal layer
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/25—Web or sheet containing structurally defined element or component and including a second component containing structurally defined particles
    • Y10T428/256—Heavy metal or aluminum or compound thereof

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Metal Substrates For Printed Circuits (AREA)
  • Casings For Electric Apparatus (AREA)
DE69115619T 1990-09-18 1991-09-09 Leiterplatte und Verfahren zu ihrer Herstellung Expired - Fee Related DE69115619T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP24612190 1990-09-18
JP3190094A JPH04355990A (ja) 1990-09-18 1991-07-30 回路基板およびその製造方法

Publications (2)

Publication Number Publication Date
DE69115619D1 true DE69115619D1 (de) 1996-02-01
DE69115619T2 DE69115619T2 (de) 1996-05-15

Family

ID=26505865

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69115619T Expired - Fee Related DE69115619T2 (de) 1990-09-18 1991-09-09 Leiterplatte und Verfahren zu ihrer Herstellung

Country Status (5)

Country Link
US (2) US5236772A (de)
EP (1) EP0476898B1 (de)
JP (1) JPH04355990A (de)
KR (1) KR950003243B1 (de)
DE (1) DE69115619T2 (de)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5619018A (en) * 1995-04-03 1997-04-08 Compaq Computer Corporation Low weight multilayer printed circuit board
US5653893A (en) * 1995-06-23 1997-08-05 Berg; N. Edward Method of forming through-holes in printed wiring board substrates
JP2000286549A (ja) 1999-03-24 2000-10-13 Fujitsu Ltd バイアコネクションを備えた基板の製造方法
DE10000972A1 (de) * 2000-01-06 2001-07-26 Siemens Ag Gedruckte Leiterplatte mit einer wärmeableitenden Aluminiumplatte und Verfahren zu ihrer Herstellung
US6951707B2 (en) * 2001-03-08 2005-10-04 Ppg Industries Ohio, Inc. Process for creating vias for circuit assemblies
US7000313B2 (en) * 2001-03-08 2006-02-21 Ppg Industries Ohio, Inc. Process for fabricating circuit assemblies using electrodepositable dielectric coating compositions
US7038142B2 (en) * 2002-01-24 2006-05-02 Fujitsu Limited Circuit board and method for fabricating the same, and electronic device
US20060213685A1 (en) * 2002-06-27 2006-09-28 Wang Alan E Single or multi-layer printed circuit board with improved edge via design
US6824959B2 (en) 2002-06-27 2004-11-30 Ppg Industries Ohio, Inc. Process for creating holes in polymeric substrates
AU2003248743A1 (en) * 2002-06-27 2004-01-19 Ppg Industries Ohio, Inc. Single or multi-layer printed circuit board with recessed or extended breakaway tabs and method of manufacture thereof
DE10335662A1 (de) * 2003-08-04 2005-03-10 Siemens Ag Detektormodul für einen Detektor zur Detektion ionisierender Strahlung sowie Detektor
US20050227049A1 (en) * 2004-03-22 2005-10-13 Boyack James R Process for fabrication of printed circuit boards
JP5170253B2 (ja) * 2008-11-20 2013-03-27 富士通株式会社 配線基板及び配線基板の製造方法

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3672849A (en) * 1969-07-07 1972-06-27 Wall Colmonoy Corp Cermet-type alloy coating on metal base
IT961375B (it) * 1971-07-14 1973-12-10 Lucas Industries Ltd Metodo per produrre disposizioni di conduttori elettrici per circuiti stampati
US4087300A (en) * 1974-01-07 1978-05-02 Edward Adler Process for producing metal-plastic laminate
US4125661A (en) * 1976-03-19 1978-11-14 Mona Industries, Inc. Laminated plates for chemical milling
JPS5335163A (en) * 1976-09-14 1978-04-01 Hitachi Chemical Co Ltd Method of producing printed circuit board substrate having through hole from metallic material
US4609586A (en) * 1984-08-02 1986-09-02 The Boeing Company Thermally conductive printed wiring board laminate
JPS62226695A (ja) * 1986-03-24 1987-10-05 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション 回路ボ−ドの製造方法
JPS62251136A (ja) * 1986-04-25 1987-10-31 三菱樹脂株式会社 金属複合積層板
JPS63170994A (ja) * 1986-05-30 1988-07-14 古河電気工業株式会社 多層プリント配線板及びその製造方法
GB8614868D0 (en) * 1986-06-18 1986-07-23 Ciba Geigy Ag Metallic patterns
DE3800682A1 (de) * 1988-01-13 1989-07-27 Bayer Ag Verfahren zur herstellung von elektrischen leiterplatten
JP2773366B2 (ja) * 1990-03-19 1998-07-09 富士通株式会社 多層配線基板の形成方法

Also Published As

Publication number Publication date
EP0476898B1 (de) 1995-12-20
EP0476898A2 (de) 1992-03-25
KR950003243B1 (ko) 1995-04-06
US5362359A (en) 1994-11-08
US5236772A (en) 1993-08-17
JPH04355990A (ja) 1992-12-09
DE69115619T2 (de) 1996-05-15
EP0476898A3 (en) 1993-02-03

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee