DE69105625T2 - Verfahren zur Herstellung von gedruckten Mehrschicht-Leiterplatten. - Google Patents

Verfahren zur Herstellung von gedruckten Mehrschicht-Leiterplatten.

Info

Publication number
DE69105625T2
DE69105625T2 DE69105625T DE69105625T DE69105625T2 DE 69105625 T2 DE69105625 T2 DE 69105625T2 DE 69105625 T DE69105625 T DE 69105625T DE 69105625 T DE69105625 T DE 69105625T DE 69105625 T2 DE69105625 T2 DE 69105625T2
Authority
DE
Germany
Prior art keywords
production
circuit boards
printed circuit
printed
multilayer printed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69105625T
Other languages
English (en)
Other versions
DE69105625D1 (de
Inventor
Takahiro Murakami
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of DE69105625D1 publication Critical patent/DE69105625D1/de
Application granted granted Critical
Publication of DE69105625T2 publication Critical patent/DE69105625T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/24—Reinforcing the conductive pattern
    • H05K3/243—Reinforcing the conductive pattern characterised by selective plating, e.g. for finish plating of pads
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4647—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits by applying an insulating layer around previously made via studs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0335—Layered conductors or foils
    • H05K2201/0347—Overplating, e.g. for reinforcing conductors or bumps; Plating over filled vias
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0364—Conductor shape
    • H05K2201/0367—Metallic bump or raised conductor not used as solder bump
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/05—Patterning and lithography; Masks; Details of resist
    • H05K2203/0502—Patterning and lithography
    • H05K2203/0505—Double exposure of the same photosensitive layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
    • H05K2203/0703—Plating
    • H05K2203/0733—Method for plating stud vias, i.e. massive vias formed by plating the bottom of a hole without plating on the walls
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
    • H05K3/061—Etching masks
    • H05K3/064—Photoresists
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49126—Assembling bases
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y10T29/49156—Manufacturing circuit on or in base with selective destruction of conductive paths

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
DE69105625T 1990-05-28 1991-05-16 Verfahren zur Herstellung von gedruckten Mehrschicht-Leiterplatten. Expired - Fee Related DE69105625T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2135505A JPH0636472B2 (ja) 1990-05-28 1990-05-28 多層配線基板の製造方法

Publications (2)

Publication Number Publication Date
DE69105625D1 DE69105625D1 (de) 1995-01-19
DE69105625T2 true DE69105625T2 (de) 1995-05-24

Family

ID=15153332

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69105625T Expired - Fee Related DE69105625T2 (de) 1990-05-28 1991-05-16 Verfahren zur Herstellung von gedruckten Mehrschicht-Leiterplatten.

Country Status (4)

Country Link
US (1) US5092032A (de)
EP (1) EP0459665B1 (de)
JP (1) JPH0636472B2 (de)
DE (1) DE69105625T2 (de)

Families Citing this family (76)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5203078A (en) * 1985-07-17 1993-04-20 Ibiden Co., Ltd. Printed wiring board for IC cards
US6568073B1 (en) 1991-11-29 2003-05-27 Hitachi Chemical Company, Ltd. Process for the fabrication of wiring board for electrical tests
DE69218344T2 (de) * 1991-11-29 1997-10-23 Hitachi Chemical Co Ltd Herstellungsverfahren für eine gedruckte Schaltung
US5504992A (en) * 1991-11-29 1996-04-09 Hitachi Chemical Company, Ltd. Fabrication process of wiring board
TW229350B (de) * 1992-08-28 1994-09-01 Hitachi Seisakusyo Kk
JP2657741B2 (ja) * 1992-11-17 1997-09-24 池上通信機株式会社 カラー画像表示方法及び装置
FR2699323B1 (fr) * 1992-12-15 1995-01-13 Asulab Sa Contacteur "reed" et procédé de fabrication de microstructures métalliques tridimensionnelles suspendues.
DE69311277T2 (de) * 1992-12-15 1998-01-15 Asulab Sa Schutzrohrschalter und Herstellungsverfahren für aufgehängte dreidimensionale metallische Mikrostrukturen
DE4310296A1 (de) * 1993-03-30 1994-10-06 Microparts Gmbh Verfahren zum Herstellen gestufter Formeinsätze, gestufte Formeinsätze und damit abgeformte gestufte Mikrostrukturkörper hoher Präzision
US5529681A (en) * 1993-03-30 1996-06-25 Microparts Gesellschaft Fur Mikrostrukturtechnik Mbh Stepped mould inserts, high-precision stepped microstructure bodies, and methods of producing the same
US5726482A (en) * 1994-02-08 1998-03-10 Prolinx Labs Corporation Device-under-test card for a burn-in board
US5808351A (en) * 1994-02-08 1998-09-15 Prolinx Labs Corporation Programmable/reprogramable structure using fuses and antifuses
US5813881A (en) * 1994-02-08 1998-09-29 Prolinx Labs Corporation Programmable cable and cable adapter using fuses and antifuses
US5917229A (en) 1994-02-08 1999-06-29 Prolinx Labs Corporation Programmable/reprogrammable printed circuit board using fuse and/or antifuse as interconnect
US5834824A (en) 1994-02-08 1998-11-10 Prolinx Labs Corporation Use of conductive particles in a nonconductive body as an integrated circuit antifuse
US5572409A (en) * 1994-02-08 1996-11-05 Prolinx Labs Corporation Apparatus including a programmable socket adapter for coupling an electronic component to a component socket on a printed circuit board
FR2721435B1 (fr) * 1994-06-17 1996-08-02 Asulab Sa Microcontacteur magnétique et son procédé de fabrication.
JP2571677B2 (ja) * 1994-11-22 1997-01-16 インターナショナル・ビジネス・マシーンズ・コーポレイション 半導体装置の製造方法
US5962815A (en) 1995-01-18 1999-10-05 Prolinx Labs Corporation Antifuse interconnect between two conducting layers of a printed circuit board
US5906042A (en) 1995-10-04 1999-05-25 Prolinx Labs Corporation Method and structure to interconnect traces of two conductive layers in a printed circuit board
US5767575A (en) 1995-10-17 1998-06-16 Prolinx Labs Corporation Ball grid array structure and method for packaging an integrated circuit chip
JPH09148731A (ja) * 1995-11-17 1997-06-06 Fujitsu Ltd 配線基板間の接続構造の製造方法
US5707893A (en) * 1995-12-01 1998-01-13 International Business Machines Corporation Method of making a circuitized substrate using two different metallization processes
US5872338A (en) 1996-04-10 1999-02-16 Prolinx Labs Corporation Multilayer board having insulating isolation rings
US6112406A (en) * 1996-05-06 2000-09-05 Siemens Aktiengesellschaft Method for producing electrically conductive connections between two or more conductor structures
JP3398557B2 (ja) * 1997-01-29 2003-04-21 インターナショナル・ビジネス・マシーンズ・コーポレーション 表層配線プリント基板の製造方法
US6222136B1 (en) 1997-11-12 2001-04-24 International Business Machines Corporation Printed circuit board with continuous connective bumps
JP2002503878A (ja) * 1997-12-05 2002-02-05 リア オートモーティヴ ディアボーン インコーポレイテッド プリント回路及び製造方法
US6063647A (en) * 1997-12-08 2000-05-16 3M Innovative Properties Company Method for making circuit elements for a z-axis interconnect
US6034427A (en) 1998-01-28 2000-03-07 Prolinx Labs Corporation Ball grid array structure and method for packaging an integrated circuit chip
US6119338A (en) * 1998-03-19 2000-09-19 Industrial Technology Research Institute Method for manufacturing high-density multilayer printed circuit boards
JP3137186B2 (ja) * 1999-02-05 2001-02-19 インターナショナル・ビジネス・マシーンズ・コーポレ−ション 層間接続構造体、多層配線基板およびそれらの形成方法
US20100044080A1 (en) * 1999-08-27 2010-02-25 Lex Kosowsky Metal Deposition
US20080035370A1 (en) * 1999-08-27 2008-02-14 Lex Kosowsky Device applications for voltage switchable dielectric material having conductive or semi-conductive organic material
US7825491B2 (en) * 2005-11-22 2010-11-02 Shocking Technologies, Inc. Light-emitting device using voltage switchable dielectric material
US7446030B2 (en) * 1999-08-27 2008-11-04 Shocking Technologies, Inc. Methods for fabricating current-carrying structures using voltage switchable dielectric materials
US20100044079A1 (en) * 1999-08-27 2010-02-25 Lex Kosowsky Metal Deposition
AU6531600A (en) * 1999-08-27 2001-03-26 Lex Kosowsky Current carrying structure using voltage switchable dielectric material
US7695644B2 (en) * 1999-08-27 2010-04-13 Shocking Technologies, Inc. Device applications for voltage switchable dielectric material having high aspect ratio particles
US6216941B1 (en) * 2000-01-06 2001-04-17 Trw Inc. Method for forming high frequency connections to high temperature superconductor circuits and other fragile materials
TW496111B (en) 2000-08-24 2002-07-21 Ind Tech Res Inst Method of forming contact hole on multi-level circuit board
US6465084B1 (en) 2001-04-12 2002-10-15 International Business Machines Corporation Method and structure for producing Z-axis interconnection assembly of printed wiring board elements
IL165282A0 (en) * 2002-05-23 2005-12-18 Schott Ag Method for producing a component comprising a conductor structure that issuitable for use at high frequencies
JP2005535108A (ja) * 2002-05-23 2005-11-17 ショット アーゲー 高周波用途に適した導体構成を有する構成要素を製造する方法
TW530377B (en) * 2002-05-28 2003-05-01 Via Tech Inc Structure of laminated substrate with high integration and method of production thereof
US7145229B2 (en) * 2002-11-14 2006-12-05 The Regents Of The University Of California Silicone metalization
EP1435765A1 (de) * 2003-01-03 2004-07-07 Ultratera Corporation Verfahren zur Bildung von Verbindungen auf einem Leitermuster auf einer gedruckten Schaltungsplatte
US7320173B2 (en) * 2003-02-06 2008-01-22 Lg Electronics Inc. Method for interconnecting multi-layer printed circuit board
US7923844B2 (en) 2005-11-22 2011-04-12 Shocking Technologies, Inc. Semiconductor devices including voltage switchable materials for over-voltage protection
US20100263200A1 (en) * 2005-11-22 2010-10-21 Lex Kosowsky Wireless communication device using voltage switchable dielectric material
US20080029405A1 (en) * 2006-07-29 2008-02-07 Lex Kosowsky Voltage switchable dielectric material having conductive or semi-conductive organic material
US7968010B2 (en) 2006-07-29 2011-06-28 Shocking Technologies, Inc. Method for electroplating a substrate
US20080032049A1 (en) * 2006-07-29 2008-02-07 Lex Kosowsky Voltage switchable dielectric material having high aspect ratio particles
JP2010521058A (ja) 2006-09-24 2010-06-17 ショッキング テクノロジーズ，インコーポレイテッド ステップ電圧応答を有する電圧切り換え可能な誘電体材料の組成及び該誘電体材料の製造方法
US20120119168A9 (en) * 2006-11-21 2012-05-17 Robert Fleming Voltage switchable dielectric materials with low band gap polymer binder or composite
JP2008182105A (ja) * 2007-01-25 2008-08-07 Toshiba Corp 半導体素子の製造方法及び半導体素子
US7793236B2 (en) * 2007-06-13 2010-09-07 Shocking Technologies, Inc. System and method for including protective voltage switchable dielectric material in the design or simulation of substrate devices
US8206614B2 (en) * 2008-01-18 2012-06-26 Shocking Technologies, Inc. Voltage switchable dielectric material having bonded particle constituents
US8203421B2 (en) * 2008-04-14 2012-06-19 Shocking Technologies, Inc. Substrate device or package using embedded layer of voltage switchable dielectric material in a vertical switching configuration
US20100047535A1 (en) * 2008-08-22 2010-02-25 Lex Kosowsky Core layer structure having voltage switchable dielectric material
WO2010033635A1 (en) * 2008-09-17 2010-03-25 Shocking Technologies, Inc. Voltage switchable dielectric material containing boron compound
US9208931B2 (en) * 2008-09-30 2015-12-08 Littelfuse, Inc. Voltage switchable dielectric material containing conductor-on-conductor core shelled particles
EP2342722A2 (de) * 2008-09-30 2011-07-13 Shocking Technologies Inc Spannungsumschaltbares dielektrisches material mit leitenden kernhüllepartikeln
US8362871B2 (en) * 2008-11-05 2013-01-29 Shocking Technologies, Inc. Geometric and electric field considerations for including transient protective material in substrate devices
US8272123B2 (en) 2009-01-27 2012-09-25 Shocking Technologies, Inc. Substrates having voltage switchable dielectric materials
US8399773B2 (en) 2009-01-27 2013-03-19 Shocking Technologies, Inc. Substrates having voltage switchable dielectric materials
US9226391B2 (en) 2009-01-27 2015-12-29 Littelfuse, Inc. Substrates having voltage switchable dielectric materials
EP2412212A1 (de) 2009-03-26 2012-02-01 Shocking Technologies Inc Komponenten mit spannungsumschaltbaren dielektrischen materialien
US9053844B2 (en) * 2009-09-09 2015-06-09 Littelfuse, Inc. Geometric configuration or alignment of protective material in a gap structure for electrical devices
US20110198544A1 (en) * 2010-02-18 2011-08-18 Lex Kosowsky EMI Voltage Switchable Dielectric Materials Having Nanophase Materials
US9320135B2 (en) * 2010-02-26 2016-04-19 Littelfuse, Inc. Electric discharge protection for surface mounted and embedded components
US9082622B2 (en) 2010-02-26 2015-07-14 Littelfuse, Inc. Circuit elements comprising ferroic materials
US9224728B2 (en) * 2010-02-26 2015-12-29 Littelfuse, Inc. Embedded protection against spurious electrical events
CN109273339B (zh) * 2018-09-18 2021-03-19 惠科股份有限公司 一种反应室、干法刻蚀设备及刻蚀方法
CN215991352U (zh) * 2019-03-29 2022-03-08 株式会社村田制作所 树脂多层基板
CN113834827B (zh) * 2020-06-24 2024-04-12 江苏长电科技股份有限公司 多层电路基板及其偏移检测方法

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3496072A (en) * 1967-06-26 1970-02-17 Control Data Corp Multilayer printed circuit board and method for manufacturing same
US3769108A (en) * 1971-12-03 1973-10-30 Bell Telephone Labor Inc Manufacture of beam-crossovers for integrated circuits
JPS60180197A (ja) * 1984-02-27 1985-09-13 宇部興産株式会社 多層プリント配線板の製造方法
US4659587A (en) * 1984-10-11 1987-04-21 Hitachi, Ltd. Electroless plating process and process for producing multilayer wiring board
JPS62263645A (ja) * 1986-05-06 1987-11-16 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション 電気的接点構造とその形成方法
US4763403A (en) * 1986-12-16 1988-08-16 Eastman Kodak Company Method of making an electronic component
JPH081987B2 (ja) * 1987-09-30 1996-01-10 日立化成工業株式会社 配線板の製造法
JP2700259B2 (ja) * 1988-10-06 1998-01-19 イビデン株式会社 プリント配線板における凹所を有する半田層の形成方法
US4920639A (en) * 1989-08-04 1990-05-01 Microelectronics And Computer Technology Corporation Method of making a multilevel electrical airbridge interconnect

Also Published As

Publication number Publication date
DE69105625D1 (de) 1995-01-19
JPH0636472B2 (ja) 1994-05-11
JPH0432295A (ja) 1992-02-04
EP0459665B1 (de) 1994-12-07
EP0459665A1 (de) 1991-12-04
US5092032A (en) 1992-03-03

Similar Documents

Publication Publication Date Title
DE69105625T2 (de) Verfahren zur Herstellung von gedruckten Mehrschicht-Leiterplatten.
DE68921732T2 (de) Verfahren zur Herstellung von gedruckten Mehrschicht-Leiterplatten.
DE69123120T2 (de) Verfahren zur Herstellung von gedruckten Leiterplatten
DE58907030D1 (de) Verfahren zur Herstellung von Leiterplatten.
DE69104750D1 (de) Verfahren zur Herstellung von Mehrschichtplatinen.
DE69204571T2 (de) Verfahren zur Herstellung von elektronischen Mehrschichtschaltungen.
DE69418698D1 (de) Verfahren zur Herstellung von Leiterplatten
DE69122573D1 (de) Verfahren zur Herstellung von Mehrschichtplatinen
DE69431828T2 (de) Verfahren zur Herstellung von gedruckten Schaltungskarten
DE68923468T2 (de) Verfahren zur Herstellung von Mehrschichtschaltungen.
DE69325936D1 (de) Verfahren zur Herstellung von Platten für gedruckte Schaltungen
DE69125233D1 (de) Verfahren zur Herstellung von gedruckten Schaltungen
DE68918975D1 (de) Verfahren für die Herstellung von Leiterplatten.
DE69220892D1 (de) Verfahren zur Herstellung von mehrschichtigen Leiterplatten aus Polyimid
DE68909853T2 (de) Verfahren und Film zur Herstellung von gedruckten Schaltungsplatten.
DE69824133D1 (de) Verfahren zur Herstellung von mehrschichtigen Leiterplatten
DE69115852D1 (de) Verfahren zur Herstellung einer Leiterplatte
DE69203544D1 (de) Verfahren zur Herstellung einer mehrschichtigen Glaskeramik-Leiterplatte.
DE69326925D1 (de) Verfahren zur Herstellung von gedruckten Leiterplatten
DE69023816T2 (de) Verfahren zur Herstellung gedruckter Schaltungsplatten.
DE69320498T2 (de) Verfahren zur Herstellung von Dünnfilm-Leiterplatten
DE59106557D1 (de) Verfahren zur Herstellung von Leiterplatten.
DE69735750D1 (de) Verfahren zur Herstellung von Leiterplatten
DE68916085T2 (de) Verfahren zur Herstellung von Leiterplatten.
DE69431175T2 (de) Verfahren zur Herstellung einer Leiterplatte

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee