DE3788527D1 - Bipolarer Transistor und sein Herstellungsverfahren. - Google Patents

Bipolarer Transistor und sein Herstellungsverfahren.

Info

Publication number
DE3788527D1
DE3788527D1 DE87302784T DE3788527T DE3788527D1 DE 3788527 D1 DE3788527 D1 DE 3788527D1 DE 87302784 T DE87302784 T DE 87302784T DE 3788527 T DE3788527 T DE 3788527T DE 3788527 D1 DE3788527 D1 DE 3788527D1
Authority
DE
Germany
Prior art keywords
manufacturing process
bipolar transistor
bipolar
transistor
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE87302784T
Other languages
English (en)
Other versions
DE3788527T2 (de
Inventor
Masanori Inada
Kazuo Eda
Yorito Ota
Atsushi Nakagawa
Manabu Yanagihara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP7473886A external-priority patent/JPH07120658B2/ja
Priority claimed from JP10793686A external-priority patent/JPH07120661B2/ja
Priority claimed from JP19329486A external-priority patent/JPS6348863A/ja
Priority claimed from JP28632386A external-priority patent/JPS63138773A/ja
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Publication of DE3788527D1 publication Critical patent/DE3788527D1/de
Application granted granted Critical
Publication of DE3788527T2 publication Critical patent/DE3788527T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234Bipolar junction transistors [BJT]
    • H01L29/6631Bipolar junction transistors [BJT] with an active layer made of a group 13/15 material
    • H01L29/66318Heterojunction transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0804Emitter regions of bipolar transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41708Emitter or collector electrodes for bipolar transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70Bipolar devices
    • H01L29/72Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73Bipolar junction transistors
    • H01L29/737Hetero-junction transistors
    • H01L29/7371Vertical transistors
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/01Bipolar transistors-ion implantation
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/072Heterojunctions

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Bipolar Transistors (AREA)
DE87302784T 1986-04-01 1987-03-31 Bipolarer Transistor und sein Herstellungsverfahren. Expired - Fee Related DE3788527T2 (de)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP7473886A JPH07120658B2 (ja) 1986-04-01 1986-04-01 ヘテロ接合バイポーラトランジスタの製造方法
JP10793686A JPH07120661B2 (ja) 1986-05-12 1986-05-12 ヘテロ接合バイポ−ラトランジスタおよびその製造方法
JP19329486A JPS6348863A (ja) 1986-08-19 1986-08-19 ヘテロ接合バイポ−ラトランジスタの製造方法
JP28632386A JPS63138773A (ja) 1986-12-01 1986-12-01 ヘテロ接合バイポ−ラトランジスタの製造方法

Publications (2)

Publication Number Publication Date
DE3788527D1 true DE3788527D1 (de) 1994-02-03
DE3788527T2 DE3788527T2 (de) 1994-05-11

Family

ID=27465729

Family Applications (2)

Application Number Title Priority Date Filing Date
DE87302784T Expired - Fee Related DE3788527T2 (de) 1986-04-01 1987-03-31 Bipolarer Transistor und sein Herstellungsverfahren.
DE3751972T Expired - Fee Related DE3751972T2 (de) 1986-04-01 1987-03-31 Bipolarer Transistor

Family Applications After (1)

Application Number Title Priority Date Filing Date
DE3751972T Expired - Fee Related DE3751972T2 (de) 1986-04-01 1987-03-31 Bipolarer Transistor

Country Status (3)

Country Link
US (2) US4965650A (de)
EP (2) EP0558100B1 (de)
DE (2) DE3788527T2 (de)

Families Citing this family (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0387010A3 (de) * 1989-03-08 1990-10-10 Matsushita Electric Industrial Co., Ltd. Bipolarer Transistor mit Heteroübergang
EP0390606A3 (de) * 1989-03-31 1991-10-09 Canon Kabushiki Kaisha Halbleitervorrichtung mit einem hinsichtlich des Emittorgebietes und/oder der Basiselektrode verbesserten Transistor
JP3210657B2 (ja) * 1989-11-27 2001-09-17 株式会社日立製作所 ヘテロ接合バイポーラトランジスタ
DE59005820D1 (de) * 1990-01-08 1994-06-30 Siemens Ag Verfahren zur Herstellung eines selbstjustierten Emitter-Basis-Komplexes.
DE69128123T2 (de) * 1990-08-31 1998-03-05 Texas Instruments Inc Verfahren zum Herstellen selbst-ausrichtender bipolarer Transistoren mit Heteroübergang
US5446294A (en) * 1991-07-31 1995-08-29 Texas Instruments Incorporated Microwave heterojunction bipolar transistors suitable for low-power, low-noise and high-power applications and method for fabricating same
US5272095A (en) * 1992-03-18 1993-12-21 Research Triangle Institute Method of manufacturing heterojunction transistors with self-aligned metal contacts
EP0562272A3 (en) * 1992-03-23 1994-05-25 Texas Instruments Inc Microwave heterojunction bipolar transistors with emitters designed for high power applications and method for fabricating same
US5318916A (en) * 1992-07-31 1994-06-07 Research Triangle Institute Symmetric self-aligned processing
US5286661A (en) * 1992-08-26 1994-02-15 Motorola, Inc. Method of forming a bipolar transistor having an emitter overhang
US5471078A (en) * 1992-09-09 1995-11-28 Texas Instruments Incorporated Self-aligned heterojunction bipolar transistor
JPH06132298A (ja) * 1992-10-14 1994-05-13 Mitsubishi Electric Corp 半導体装置の製造方法
US5434091A (en) * 1992-10-30 1995-07-18 Texas Instruments Incorporated Method for making collector up bipolar transistors having reducing junction capacitance and increasing current gain
US5700701A (en) * 1992-10-30 1997-12-23 Texas Instruments Incorporated Method for reducing junction capacitance and increasing current gain in collector-up bipolar transistors
US5455440A (en) * 1992-12-09 1995-10-03 Texas Instruments Incorporated Method to reduce emitter-base leakage current in bipolar transistors
US5266505A (en) * 1992-12-22 1993-11-30 International Business Machines Corporation Image reversal process for self-aligned implants in planar epitaxial-base bipolar transistors
FR2711451B1 (fr) * 1993-10-18 1995-11-17 Jackie Etrillard Procédé d'obtention de contacts conducteurs auto-alignés pour composants électroniques.
US5436181A (en) * 1994-04-18 1995-07-25 Texas Instruments Incorporated Method of self aligning an emitter contact in a heterojunction bipolar transistor
US5698460A (en) * 1994-04-20 1997-12-16 Texas Instruments Incorporated Method of self-aligning an emitter contact in a planar heterojunction bipolar transistor and apparatus thereof
US5445976A (en) * 1994-08-09 1995-08-29 Texas Instruments Incorporated Method for producing bipolar transistor having reduced base-collector capacitance
US5804487A (en) * 1996-07-10 1998-09-08 Trw Inc. Method of fabricating high βHBT devices
JPH10199896A (ja) * 1997-01-07 1998-07-31 Fujitsu Ltd 半導体装置の製造方法および半導体装置
FR2764118B1 (fr) * 1997-05-30 2000-08-04 Thomson Csf Transistor bipolaire stabilise avec elements isolants electriques
FR2803102B1 (fr) 1999-12-23 2002-03-22 Thomson Csf Transistor bipolaire a heterojonction a collecteur en haut et procede de realisation
US6552374B2 (en) * 2001-01-17 2003-04-22 Asb, Inc. Method of manufacturing bipolar device and structure thereof
US6841795B2 (en) * 2002-10-25 2005-01-11 The University Of Connecticut Semiconductor devices employing at least one modulation doped quantum well structure and one or more etch stop layers for accurate contact formation
US7190047B2 (en) * 2004-06-03 2007-03-13 Lucent Technologies Inc. Transistors and methods for making the same
US8841750B2 (en) 2012-07-18 2014-09-23 International Business Machines Corporation Local wiring for a bipolar junction transistor including a self-aligned emitter region
EP3506000B1 (de) * 2017-12-29 2020-10-07 IMEC vzw Iii-v-halbleiterwellenleiter-nanogratstruktur
JP2020120080A (ja) * 2019-01-28 2020-08-06 株式会社村田製作所 半導体素子
CN110120344B (zh) * 2019-04-09 2022-08-16 上海华虹宏力半导体制造有限公司 一种在锗硅hbt中用氮化硅侧墙实现自对准结构的方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4593305A (en) * 1983-05-17 1986-06-03 Kabushiki Kaisha Toshiba Heterostructure bipolar transistor
US4617724A (en) * 1983-06-30 1986-10-21 Fujitsu Limited Process for fabricating heterojunction bipolar transistor with low base resistance
JPS6095966A (ja) * 1983-10-31 1985-05-29 Fujitsu Ltd ヘテロ接合バイポ−ラトランジスタとその製造方法
US4593457A (en) * 1984-12-17 1986-06-10 Motorola, Inc. Method for making gallium arsenide NPN transistor with self-aligned base enhancement to emitter region and metal contact
JPS61147571A (ja) * 1984-12-21 1986-07-05 Toshiba Corp ヘテロ接合バイポ−ラトランジスタの製造方法
US4706378A (en) * 1985-01-30 1987-11-17 Texas Instruments Incorporated Method of making vertical bipolar transistor having base above buried nitride dielectric formed by deep implantation

Also Published As

Publication number Publication date
DE3751972D1 (de) 1997-01-16
EP0240307A2 (de) 1987-10-07
US4965650A (en) 1990-10-23
DE3751972T2 (de) 1997-05-22
US5166081A (en) 1992-11-24
EP0240307A3 (en) 1989-12-27
EP0558100A3 (en) 1994-07-13
EP0240307B1 (de) 1993-12-22
EP0558100A2 (de) 1993-09-01
DE3788527T2 (de) 1994-05-11
EP0558100B1 (de) 1996-12-04

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee