DE3853313T2 - Integrierter Transistor und sein Herstellungsverfahren. - Google Patents

Integrierter Transistor und sein Herstellungsverfahren.

Info

Publication number
DE3853313T2
DE3853313T2 DE19883853313 DE3853313T DE3853313T2 DE 3853313 T2 DE3853313 T2 DE 3853313T2 DE 19883853313 DE19883853313 DE 19883853313 DE 3853313 T DE3853313 T DE 3853313T DE 3853313 T2 DE3853313 T2 DE 3853313T2
Authority
DE
Germany
Prior art keywords
manufacturing process
integrated transistor
transistor
integrated
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE19883853313
Other languages
English (en)
Other versions
DE3853313D1 (de
Inventor
Ashok K Kapoor
Frank J Ciacchella
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fairchild Semiconductor Corp
Original Assignee
Fairchild Semiconductor Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fairchild Semiconductor Corp filed Critical Fairchild Semiconductor Corp
Publication of DE3853313D1 publication Critical patent/DE3853313D1/de
Application granted granted Critical
Publication of DE3853313T2 publication Critical patent/DE3853313T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1004—Base region of bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42304—Base electrodes for bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
    • H01L29/732—Vertical transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Bipolar Transistors (AREA)
  • Bipolar Integrated Circuits (AREA)
DE19883853313 1987-04-14 1988-04-12 Integrierter Transistor und sein Herstellungsverfahren. Expired - Fee Related DE3853313T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US3816187A 1987-04-14 1987-04-14

Publications (2)

Publication Number Publication Date
DE3853313D1 DE3853313D1 (de) 1995-04-20
DE3853313T2 true DE3853313T2 (de) 1995-11-16

Family

ID=21898396

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19883853313 Expired - Fee Related DE3853313T2 (de) 1987-04-14 1988-04-12 Integrierter Transistor und sein Herstellungsverfahren.

Country Status (4)

Country Link
EP (1) EP0287318B1 (de)
JP (1) JPH0198261A (de)
CA (1) CA1312679C (de)
DE (1) DE3853313T2 (de)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03201264A (ja) * 1989-12-27 1991-09-03 Sony Corp 光ディスク装置
DE4445565C2 (de) * 1994-12-20 2002-10-24 Korea Electronics Telecomm Säulen-Bipolartransistor und Verfahren zu seiner Herstellung
DE19526691A1 (de) * 1995-07-21 1997-01-23 Bosch Gmbh Robert Verfahren zur Herstellung von Beschleunigungssensoren
DE10159414A1 (de) 2001-12-04 2003-06-18 Infineon Technologies Ag Bipolar-Transistor und Verfahren zum Herstellen desselben
WO2010076825A1 (en) * 2008-12-30 2010-07-08 Fabio Pellizer Double patterning method for creating a regular array of pillars with dual shallow trench isolation
BE1018563A4 (nl) 2009-01-09 2011-03-01 Dredging Int Snijkop voor het baggeren van ondergrond en gebruik van deze snijkop voor het baggeren van ondergrond.

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3600651A (en) * 1969-12-08 1971-08-17 Fairchild Camera Instr Co Bipolar and field-effect transistor using polycrystalline epitaxial deposited silicon
JPS59186368A (ja) * 1983-04-06 1984-10-23 Matsushita Electric Ind Co Ltd 半導体装置の製造方法
JPS6132573A (ja) * 1984-07-25 1986-02-15 Matsushita Electric Ind Co Ltd 半導体集積回路装置およびその製造方法
JPS61164262A (ja) * 1985-01-17 1986-07-24 Toshiba Corp 半導体装置

Also Published As

Publication number Publication date
JPH0198261A (ja) 1989-04-17
EP0287318B1 (de) 1995-03-15
EP0287318A2 (de) 1988-10-19
DE3853313D1 (de) 1995-04-20
CA1312679C (en) 1993-01-12
EP0287318A3 (de) 1991-03-13

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee