DE3786434T2 - Speicheranordnung mit zwei multiplexierten E/A-Leitungspaaren. - Google Patents

Speicheranordnung mit zwei multiplexierten E/A-Leitungspaaren.

Info

Publication number
DE3786434T2
DE3786434T2 DE87113095T DE3786434T DE3786434T2 DE 3786434 T2 DE3786434 T2 DE 3786434T2 DE 87113095 T DE87113095 T DE 87113095T DE 3786434 T DE3786434 T DE 3786434T DE 3786434 T2 DE3786434 T2 DE 3786434T2
Authority
DE
Germany
Prior art keywords
bus
output state
precharge
data bus
cas
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE87113095T
Other languages
German (de)
English (en)
Other versions
DE3786434D1 (de
Inventor
Daeje Chin
Wei Hwang
Nicky Chau-Chun Lu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE3786434D1 publication Critical patent/DE3786434D1/de
Publication of DE3786434T2 publication Critical patent/DE3786434T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1018—Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters
    • G11C7/1021—Page serial bit line access mode, i.e. using an enabled row address stroke pulse with its associated word line address and a sequence of enabled column address stroke pulses each with its associated bit line address
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/103—Read-write modes for single port memories, i.e. having either a random port or a serial port using serially addressed read-write data registers
    • G11C7/1033—Read-write modes for single port memories, i.e. having either a random port or a serial port using serially addressed read-write data registers using data registers of which only one stage is addressed for sequentially outputting data from a predetermined number of stages, e.g. nibble read-write mode
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1048—Data bus control circuits, e.g. precharging, presetting, equalising

Landscapes

  • Engineering & Computer Science (AREA)
  • Databases & Information Systems (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
DE87113095T 1986-09-16 1987-09-08 Speicheranordnung mit zwei multiplexierten E/A-Leitungspaaren. Expired - Fee Related DE3786434T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/908,440 US4754433A (en) 1986-09-16 1986-09-16 Dynamic ram having multiplexed twin I/O line pairs

Publications (2)

Publication Number Publication Date
DE3786434D1 DE3786434D1 (de) 1993-08-12
DE3786434T2 true DE3786434T2 (de) 1994-01-20

Family

ID=25425807

Family Applications (1)

Application Number Title Priority Date Filing Date
DE87113095T Expired - Fee Related DE3786434T2 (de) 1986-09-16 1987-09-08 Speicheranordnung mit zwei multiplexierten E/A-Leitungspaaren.

Country Status (4)

Country Link
US (1) US4754433A (enrdf_load_stackoverflow)
EP (1) EP0260578B1 (enrdf_load_stackoverflow)
JP (1) JPS6378396A (enrdf_load_stackoverflow)
DE (1) DE3786434T2 (enrdf_load_stackoverflow)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5237532A (en) * 1986-06-30 1993-08-17 Kabushiki Kaisha Toshiba Serially-accessed type memory device for providing an interleaved data read operation
JP2569538B2 (ja) * 1987-03-17 1997-01-08 ソニー株式会社 メモリ装置
US4875196A (en) * 1987-09-08 1989-10-17 Sharp Microelectronic Technology, Inc. Method of operating data buffer apparatus
US5226147A (en) 1987-11-06 1993-07-06 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device for simple cache system
US5034917A (en) * 1988-05-26 1991-07-23 Bland Patrick M Computer system including a page mode memory with decreased access time and method of operation thereof
CA1314990C (en) * 1988-12-05 1993-03-23 Richard C. Foss Addressing for large dynamic ram
JP2646032B2 (ja) * 1989-10-14 1997-08-25 三菱電機株式会社 Ｌｉｆｏ方式の半導体記憶装置およびその制御方法
US4984214A (en) * 1989-12-05 1991-01-08 International Business Machines Corporation Multiplexed serial register architecture for VRAM
US5134616A (en) * 1990-02-13 1992-07-28 International Business Machines Corporation Dynamic ram with on-chip ecc and optimized bit and word redundancy
IL96808A (en) 1990-04-18 1996-03-31 Rambus Inc Introductory / Origin Circuit Agreed Using High-Performance Brokerage
US6751696B2 (en) 1990-04-18 2004-06-15 Rambus Inc. Memory device having a programmable register
US5487048A (en) * 1993-03-31 1996-01-23 Sgs-Thomson Microelectronics, Inc. Multiplexing sense amplifier
US5377143A (en) * 1993-03-31 1994-12-27 Sgs-Thomson Microelectronics, Inc. Multiplexing sense amplifier having level shifter circuits
US5517671A (en) * 1993-07-30 1996-05-14 Dell Usa, L.P. System for designating a plurality of I/O devices to a plurality of I/O channels and connecting and buffering the plurality of I/O channels to a single system bus
KR960006271B1 (ko) * 1993-08-14 1996-05-13 삼성전자주식회사 고속동작을 위한 입출력라인구동방식을 가지는 반도체메모리장치
US5694143A (en) 1994-06-02 1997-12-02 Accelerix Limited Single chip frame buffer and graphics accelerator
WO1995035572A1 (en) 1994-06-20 1995-12-28 Neomagic Corporation Graphics controller integrated circuit without memory interface
US6097388A (en) * 1995-08-22 2000-08-01 International Business Machines Corporation Method for managing non-rectangular windows in a raster display
JP3569417B2 (ja) * 1996-07-19 2004-09-22 株式会社ルネサステクノロジ 半導体メモリ
US6072746A (en) * 1998-08-14 2000-06-06 International Business Machines Corporation Self-timed address decoder for register file and compare circuit of a multi-port CAM
KR100334574B1 (ko) * 2000-01-31 2002-05-03 윤종용 풀-페이지 모드를 갖는 버스트-타입의 반도체 메모리 장치

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4156938A (en) * 1975-12-29 1979-05-29 Mostek Corporation MOSFET Memory chip with single decoder and bi-level interconnect lines
JPS53134337A (en) * 1977-03-25 1978-11-22 Hitachi Ltd Sense circuit
JPS57150190A (en) * 1981-02-27 1982-09-16 Hitachi Ltd Monolithic storage device
DE3319980A1 (de) * 1983-06-01 1984-12-06 Siemens AG, 1000 Berlin und 8000 München Integrierbares busorientiertes uebertragungssystem
JPS6059592A (ja) * 1983-09-13 1985-04-05 Nec Corp ダイナミツクランダムアクセスメモリ
JPS61233496A (ja) * 1985-04-08 1986-10-17 Nec Corp 半導体記憶装置
JPS61233495A (ja) * 1985-04-08 1986-10-17 Nec Corp 半導体記憶装置

Also Published As

Publication number Publication date
US4754433A (en) 1988-06-28
JPS6378396A (ja) 1988-04-08
JPH0437515B2 (enrdf_load_stackoverflow) 1992-06-19
EP0260578A3 (en) 1990-03-07
EP0260578A2 (en) 1988-03-23
EP0260578B1 (en) 1993-07-07
DE3786434D1 (de) 1993-08-12

Similar Documents

Publication Publication Date Title
DE3786434T2 (de) Speicheranordnung mit zwei multiplexierten E/A-Leitungspaaren.
DE69024773T2 (de) Halbleiterspeicherschaltungsanordnung
DE3588247T2 (de) Dynamischer Halbleiterspeicher mit einer statischen Datenspeicherzelle
DE3780621T2 (de) Dynamischer ram-speicher.
DE69907250T2 (de) Verfahren und anordnung zur verlängerung der verfügbaren auffrischungszeit eines 1-t sram-kompatibelspeichers
DE69630858T2 (de) Vorladungsschaltung für eine Halbleiterspeicheranordnung
DE3889097T2 (de) Halbleiterspeicheranordnung.
DE69923634T2 (de) Synchrone Burstzugriffshalbleiterspeicheranordnung
DE4236453C2 (de) Mehrkanal-Speichereinrichtung und Verfahren zum Betreiben derselben
DE69838776T2 (de) Signalübertragungssystem
DE69621280T2 (de) Speichergerätschaltkreis und Verfahren zur gleichzeitigen Adressierung der Spalten einer Vielzahl von Banken einer Vielzahlbankspeicheranordnung
DE4214970C2 (de) Halbleiterspeichereinrichtung und Betriebsverfahren dafür
DE3923629C2 (de) DRAM-Halbleiterbaustein
DE69120448T2 (de) Halbleiterspeicheranordnungen von dynamischem Typus
DE3884022T2 (de) Halbleiterspeicheranordnung.
DE69025520T2 (de) Speicher mit verbessertem Bitzeilenausgleich
DE69414760T2 (de) Halbleiter-Speichervorrichtung
DE69619794T2 (de) Speicherzelle zum lesen und schreiben einer registerbank
DE3533870C2 (enrdf_load_stackoverflow)
DE3783666T2 (de) Halbleiterspeicheranordnung.
DE69420771T2 (de) Adressenpuffer
DE102008049062A1 (de) Speicherzelle, Speicherbaustein, Baustein und Verfahren zum Zugreifen auf eine Speicherzelle
DE69220101T2 (de) Halbleiterspeichereinrichtung
DE4428647A1 (de) Halbleiterspeicherbauelement mit einer Struktur zur Ansteuerung von Eingabe/Ausgabeleitungen mit hoher Geschwindigkeit
DE68909626T2 (de) Dekodierschaltung.

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee