DE3782406T2 - Plastikverpackung fuer hochfrequenz-halbleiteranordnungen. - Google Patents

Plastikverpackung fuer hochfrequenz-halbleiteranordnungen.

Info

Publication number
DE3782406T2
DE3782406T2 DE8787402883T DE3782406T DE3782406T2 DE 3782406 T2 DE3782406 T2 DE 3782406T2 DE 8787402883 T DE8787402883 T DE 8787402883T DE 3782406 T DE3782406 T DE 3782406T DE 3782406 T2 DE3782406 T2 DE 3782406T2
Authority
DE
Germany
Prior art keywords
frequency semiconductor
plastic packing
semiconductor arrangements
arrangements
packing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8787402883T
Other languages
English (en)
Other versions
DE3782406D1 (de
Inventor
William S Phy
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fairchild Semiconductor Corp
Original Assignee
Fairchild Semiconductor Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fairchild Semiconductor Corp filed Critical Fairchild Semiconductor Corp
Application granted granted Critical
Publication of DE3782406D1 publication Critical patent/DE3782406D1/de
Publication of DE3782406T2 publication Critical patent/DE3782406T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)
DE8787402883T 1986-12-17 1987-12-17 Plastikverpackung fuer hochfrequenz-halbleiteranordnungen. Expired - Fee Related DE3782406T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/943,339 US4791473A (en) 1986-12-17 1986-12-17 Plastic package for high frequency semiconductor devices

Publications (2)

Publication Number Publication Date
DE3782406D1 DE3782406D1 (de) 1992-12-03
DE3782406T2 true DE3782406T2 (de) 1993-05-06

Family

ID=25479483

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8787402883T Expired - Fee Related DE3782406T2 (de) 1986-12-17 1987-12-17 Plastikverpackung fuer hochfrequenz-halbleiteranordnungen.

Country Status (5)

Country Link
US (1) US4791473A (de)
EP (1) EP0272187B1 (de)
JP (1) JPS63192260A (de)
KR (1) KR960002497B1 (de)
DE (1) DE3782406T2 (de)

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US4863806A (en) * 1985-06-25 1989-09-05 Hewlett-Packard Company Optical isolator
US5148243A (en) * 1985-06-25 1992-09-15 Hewlett-Packard Company Optical isolator with encapsulation
JP2522524B2 (ja) * 1988-08-06 1996-08-07 株式会社東芝 半導体装置の製造方法
US5099306A (en) * 1988-11-21 1992-03-24 Honeywell Inc. Stacked tab leadframe assembly
US5183711A (en) * 1988-12-13 1993-02-02 Shinko Electric Industries Co., Ltd. Automatic bonding tape used in semiconductor device
US4965654A (en) * 1989-10-30 1990-10-23 International Business Machines Corporation Semiconductor package with ground plane
US5008615A (en) * 1989-11-03 1991-04-16 Motorola, Inc. Means and method for testing integrated circuits attached to a leadframe
JPH05218281A (ja) * 1992-02-07 1993-08-27 Texas Instr Japan Ltd 半導体装置
US5386141A (en) * 1992-03-31 1995-01-31 Vlsi Technology, Inc. Leadframe having one or more power/ground planes without vias
US5376909A (en) * 1992-05-29 1994-12-27 Texas Instruments Incorporated Device packaging
JP3088193B2 (ja) * 1992-06-05 2000-09-18 三菱電機株式会社 Ｌｏｃ構造を有する半導体装置の製造方法並びにこれに使用するリードフレーム
DE4345301C2 (de) * 1992-06-05 2003-11-20 Mitsubishi Electric Corp Zuführungsdraht-Rahmen zur Verwendung bei der Herstellung einer Halbleitervorrichtung mit LOC-Struktur und Verfahren zum Herstellen einer Halbleitervorrichtung mit LOC-Struktur
KR100306988B1 (ko) * 1992-10-26 2001-12-15 윌리엄 비. 켐플러 장치패키지
US5457340A (en) * 1992-12-07 1995-10-10 Integrated Device Technology, Inc. Leadframe with power and ground planes
US5442225A (en) * 1993-08-13 1995-08-15 Lsi Logic Corporation Integrated circuit having interconnects with ringing suppressing elements
EP0668615A1 (de) * 1994-02-18 1995-08-23 Siemens Aktiengesellschaft Kunststoff-SMD-Gehäuse für einen Halbleiterchip
US5485029A (en) * 1994-06-30 1996-01-16 International Business Machines Corporation On-chip ground plane for semiconductor devices to reduce parasitic signal propagation
US5714792A (en) * 1994-09-30 1998-02-03 Motorola, Inc. Semiconductor device having a reduced die support area and method for making the same
US5541565A (en) * 1995-05-22 1996-07-30 Trw Inc. High frequency microelectronic circuit enclosure
US5969293A (en) * 1997-07-18 1999-10-19 National Semiconductor Corporation Method and apparatus for doubling back single gauge lead frame
US6075283A (en) * 1998-07-06 2000-06-13 Micron Technology, Inc. Downset lead frame for semiconductor packages
JP3444410B2 (ja) * 2000-03-23 2003-09-08 株式会社三井ハイテック リードフレームおよび半導体装置の製造方法
US6246312B1 (en) 2000-07-20 2001-06-12 Cts Corporation Ball grid array resistor terminator network
SG112799A1 (en) 2000-10-09 2005-07-28 St Assembly Test Services Ltd Leaded semiconductor packages and method of trimming and singulating such packages
US6686258B2 (en) 2000-11-02 2004-02-03 St Assembly Test Services Ltd. Method of trimming and singulating leaded semiconductor packages
US6777786B2 (en) * 2001-03-12 2004-08-17 Fairchild Semiconductor Corporation Semiconductor device including stacked dies mounted on a leadframe
US7038305B1 (en) 2003-07-15 2006-05-02 Altera Corp. Package for integrated circuit die
US7180186B2 (en) * 2003-07-31 2007-02-20 Cts Corporation Ball grid array package
US6946733B2 (en) * 2003-08-13 2005-09-20 Cts Corporation Ball grid array package having testing capability after mounting
US7196313B2 (en) * 2004-04-02 2007-03-27 Fairchild Semiconductor Corporation Surface mount multi-channel optocoupler
AT504250A2 (de) 2005-06-30 2008-04-15 Fairchild Semiconductor Halbleiterchip-packung und verfahren zur herstellung derselben
US20090057852A1 (en) * 2007-08-27 2009-03-05 Madrid Ruben P Thermally enhanced thin semiconductor package
US20070164428A1 (en) * 2006-01-18 2007-07-19 Alan Elbanhawy High power module with open frame package
US7868432B2 (en) * 2006-02-13 2011-01-11 Fairchild Semiconductor Corporation Multi-chip module for battery power control
US7768075B2 (en) 2006-04-06 2010-08-03 Fairchild Semiconductor Corporation Semiconductor die packages using thin dies and metal substrates
US7656024B2 (en) 2006-06-30 2010-02-02 Fairchild Semiconductor Corporation Chip module for complete power train
US7564124B2 (en) * 2006-08-29 2009-07-21 Fairchild Semiconductor Corporation Semiconductor die package including stacked dice and heat sink structures
US7821116B2 (en) * 2007-02-05 2010-10-26 Fairchild Semiconductor Corporation Semiconductor die package including leadframe with die attach pad with folded edge
US7659531B2 (en) * 2007-04-13 2010-02-09 Fairchild Semiconductor Corporation Optical coupler package
US7902657B2 (en) * 2007-08-28 2011-03-08 Fairchild Semiconductor Corporation Self locking and aligning clip structure for semiconductor die package
US20090057855A1 (en) * 2007-08-30 2009-03-05 Maria Clemens Quinones Semiconductor die package including stand off structures
US20090140266A1 (en) * 2007-11-30 2009-06-04 Yong Liu Package including oriented devices
US7589338B2 (en) * 2007-11-30 2009-09-15 Fairchild Semiconductor Corporation Semiconductor die packages suitable for optoelectronic applications having clip attach structures for angled mounting of dice
KR20090062612A (ko) * 2007-12-13 2009-06-17 페어차일드코리아반도체 주식회사 멀티 칩 패키지
US20090166826A1 (en) * 2007-12-27 2009-07-02 Janducayan Omar A Lead frame die attach paddles with sloped walls and backside grooves suitable for leadless packages
US8106406B2 (en) 2008-01-09 2012-01-31 Fairchild Semiconductor Corporation Die package including substrate with molded device
US20090194856A1 (en) * 2008-02-06 2009-08-06 Gomez Jocel P Molded package assembly
KR101524545B1 (ko) * 2008-02-28 2015-06-01 페어차일드코리아반도체 주식회사 전력 소자 패키지 및 그 제조 방법
US7768108B2 (en) 2008-03-12 2010-08-03 Fairchild Semiconductor Corporation Semiconductor die package including embedded flip chip
US8018054B2 (en) * 2008-03-12 2011-09-13 Fairchild Semiconductor Corporation Semiconductor die package including multiple semiconductor dice
KR101519062B1 (ko) * 2008-03-31 2015-05-11 페어차일드코리아반도체 주식회사 반도체 소자 패키지
US20090278241A1 (en) * 2008-05-08 2009-11-12 Yong Liu Semiconductor die package including die stacked on premolded substrate including die
US8193618B2 (en) 2008-12-12 2012-06-05 Fairchild Semiconductor Corporation Semiconductor die package with clip interconnection
US7973393B2 (en) 2009-02-04 2011-07-05 Fairchild Semiconductor Corporation Stacked micro optocouplers and methods of making the same
US8421204B2 (en) 2011-05-18 2013-04-16 Fairchild Semiconductor Corporation Embedded semiconductor power modules and packages

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US4252864A (en) * 1979-11-05 1981-02-24 Amp Incorporated Lead frame having integral terminal tabs
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US4551746A (en) * 1982-10-05 1985-11-05 Mayo Foundation Leadless chip carrier apparatus providing an improved transmission line environment and improved heat dissipation
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IT1212711B (it) * 1983-03-09 1989-11-30 Ates Componenti Elettron Dispositivo a semiconduttore aforma di scheda piana con contatti elettrici su ambedue le facce eprocedimento per la sua fabbricazione.
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US4651415A (en) * 1985-03-22 1987-03-24 Diacon, Inc. Leaded chip carrier

Also Published As

Publication number Publication date
EP0272187B1 (de) 1992-10-28
DE3782406D1 (de) 1992-12-03
JPS63192260A (ja) 1988-08-09
EP0272187A3 (en) 1988-08-31
KR960002497B1 (ko) 1996-02-17
EP0272187A2 (de) 1988-06-22
KR880008440A (ko) 1988-08-31
US4791473A (en) 1988-12-13

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