DE3715092A1 - Verfahren zur herstellung einer halbleiteranordnung - Google Patents

Verfahren zur herstellung einer halbleiteranordnung

Info

Publication number
DE3715092A1
DE3715092A1 DE19873715092 DE3715092A DE3715092A1 DE 3715092 A1 DE3715092 A1 DE 3715092A1 DE 19873715092 DE19873715092 DE 19873715092 DE 3715092 A DE3715092 A DE 3715092A DE 3715092 A1 DE3715092 A1 DE 3715092A1
Authority
DE
Germany
Prior art keywords
film
semiconductor substrate
recess
oxide film
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
DE19873715092
Other languages
German (de)
English (en)
Other versions
DE3715092C2 (https=
Inventor
Isamu Namose
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP62053453A external-priority patent/JPS63184352A/ja
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Publication of DE3715092A1 publication Critical patent/DE3715092A1/de
Application granted granted Critical
Publication of DE3715092C2 publication Critical patent/DE3715092C2/de
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H10W10/0143—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations comprising concurrently refilling multiple trenches having different shapes or dimensions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/012—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H10W10/0145—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations of trenches having shapes other than rectangular or V-shape
    • H10W10/0147—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations of trenches having shapes other than rectangular or V-shape the shapes being altered by a local oxidation of silicon process, e.g. trench corner rounding by LOCOS
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H10W10/0148—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations comprising introducing impurities in side walls or bottom walls of trenches, e.g. for forming channel stoppers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/13—Isolation regions comprising dielectric materials formed using local oxidation of silicon [LOCOS], e.g. sealed interface localised oxidation [SILO] or side-wall mask isolation [SWAMI]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/17—Isolation regions comprising dielectric materials formed using trench refilling with dielectric materials, e.g. shallow trench isolations

Landscapes

  • Element Separation (AREA)
DE19873715092 1986-05-09 1987-05-06 Verfahren zur herstellung einer halbleiteranordnung Granted DE3715092A1 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP10596586 1986-05-09
JP22770986 1986-09-26
JP62053453A JPS63184352A (ja) 1986-05-09 1987-03-09 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
DE3715092A1 true DE3715092A1 (de) 1987-11-12
DE3715092C2 DE3715092C2 (https=) 1993-07-29

Family

ID=27294953

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19873715092 Granted DE3715092A1 (de) 1986-05-09 1987-05-06 Verfahren zur herstellung einer halbleiteranordnung

Country Status (6)

Country Link
DE (1) DE3715092A1 (https=)
FR (1) FR2598557B1 (https=)
GB (1) GB2190241B (https=)
HK (1) HK28791A (https=)
NL (1) NL190591C (https=)
SG (1) SG60090G (https=)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4118471A1 (de) * 1990-06-06 1991-12-12 Mitsubishi Electric Corp Verfahren zur herstellung einer grabentrennstruktur
DE4121129A1 (de) * 1991-04-09 1992-10-22 Samsung Electronics Co Ltd Elementisolationsverfahren fuer halbleitervorrichtungen
DE19700854A1 (de) * 1996-06-26 1998-01-02 Lg Semicon Co Ltd Verfahren zur Herstellung einer Isolationsschicht für eine Halbleitereinrichtung

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1189143B (it) * 1986-05-16 1988-01-28 Sgs Microelettronica Spa Procedimento per la realizzazione dell'isolamento di circuiti integrati a elevatissima scala d'integrazione,in particolare in tecnologia mos e cmos
JPH0574927A (ja) * 1991-09-13 1993-03-26 Nec Corp 半導体装置の製造方法
KR0147630B1 (ko) * 1995-04-21 1998-11-02 김광호 반도체 장치의 소자분리방법
CN102683290A (zh) * 2011-03-08 2012-09-19 无锡华润上华半导体有限公司 Rom器件及其制造方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2133978A1 (de) * 1970-07-10 1972-01-13 Philips Nv Verfahren zur Herstellung einer Halb leiteranordnung und durch dieses Verfahren hergestellte Halbleiteranordnung
JPS5578540A (en) * 1978-12-08 1980-06-13 Hitachi Ltd Manufacture of semiconductor device
JPS5694647A (en) * 1979-12-28 1981-07-31 Fujitsu Ltd Forming method for oxidized film
JPS5694646A (en) * 1979-12-28 1981-07-31 Fujitsu Ltd Forming method for oxidized film
JPS5893342A (ja) * 1981-11-30 1983-06-03 Toshiba Corp 半導体装置の製造方法
US4546538A (en) * 1983-09-05 1985-10-15 Oki Electric Industry Co., Ltd. Method of manufacturing semiconductor integrated circuit devices having dielectric isolation regions

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4238278A (en) * 1979-06-14 1980-12-09 International Business Machines Corporation Polycrystalline silicon oxidation method for making shallow and deep isolation trenches
US4394196A (en) * 1980-07-16 1983-07-19 Tokyo Shibaura Denki Kabushiki Kaisha Method of etching, refilling and etching dielectric grooves for isolating micron size device regions
US4435446A (en) * 1982-11-15 1984-03-06 Hewlett-Packard Company Edge seal with polysilicon in LOCOS process

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2133978A1 (de) * 1970-07-10 1972-01-13 Philips Nv Verfahren zur Herstellung einer Halb leiteranordnung und durch dieses Verfahren hergestellte Halbleiteranordnung
JPS5578540A (en) * 1978-12-08 1980-06-13 Hitachi Ltd Manufacture of semiconductor device
JPS5694647A (en) * 1979-12-28 1981-07-31 Fujitsu Ltd Forming method for oxidized film
JPS5694646A (en) * 1979-12-28 1981-07-31 Fujitsu Ltd Forming method for oxidized film
JPS5893342A (ja) * 1981-11-30 1983-06-03 Toshiba Corp 半導体装置の製造方法
US4546538A (en) * 1983-09-05 1985-10-15 Oki Electric Industry Co., Ltd. Method of manufacturing semiconductor integrated circuit devices having dielectric isolation regions

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4118471A1 (de) * 1990-06-06 1991-12-12 Mitsubishi Electric Corp Verfahren zur herstellung einer grabentrennstruktur
DE4121129A1 (de) * 1991-04-09 1992-10-22 Samsung Electronics Co Ltd Elementisolationsverfahren fuer halbleitervorrichtungen
DE19700854A1 (de) * 1996-06-26 1998-01-02 Lg Semicon Co Ltd Verfahren zur Herstellung einer Isolationsschicht für eine Halbleitereinrichtung
DE19700854B4 (de) * 1996-06-26 2007-04-05 LG Semicon Co., Ltd., Cheongju Verfahren zur Herstellung einer Isolationsschicht für eine Halbleitereinrichtung

Also Published As

Publication number Publication date
FR2598557A1 (fr) 1987-11-13
FR2598557B1 (fr) 1990-03-30
GB2190241B (en) 1989-12-13
NL190591C (nl) 1994-05-02
GB8710281D0 (en) 1987-06-03
SG60090G (en) 1990-09-07
GB2190241A (en) 1987-11-11
DE3715092C2 (https=) 1993-07-29
NL8701087A (nl) 1987-12-01
HK28791A (en) 1991-04-26
NL190591B (nl) 1993-12-01

Similar Documents

Publication Publication Date Title
DE3751920T2 (de) Isolationsverfahren für integrierte Schaltungen
EP0010624B1 (de) Verfahren zur Ausbildung sehr kleiner Maskenöffnungen für die Herstellung von Halbleiterschaltungsanordnungen
EP0000327B1 (de) Verfahren zum Herstellen von integrierten Halbleiteranordnungen durch Anwendung einer auf Selbstausrichtung basierenden Maskierungstechnik
DE3485880T2 (de) Verfahren zur herstellung von halbleiteranordnungen.
EP0001100B1 (de) Verfahren zum Herstellen von in Silicium eingelegten dielektrischen Isolationsbereichen mittels geladener und beschleunigter Teilchen
DE4235534C2 (de) Verfahren zum Isolieren von Feldeffekttransistoren
EP0010596B1 (de) Verfahren zur Ausbildung von Maskenöffnungen bei der Herstellung von Halbleiteranordnungen
DE3327301C2 (de) Verfahren zur Herstellung einer integrierten Halbleiterschaltung
DE3587829T2 (de) Verfahren zur herstellung von untereinander selbstalignierten gräben unter verwendung einer maske.
DE4109184C2 (de) Verfahren zum Bilden einer Feldoxidschicht eines Halbleiterbauteils
EP0030640B1 (de) Verfahren zum Anbringen einer selbstausrichtenden Gateelektrode in einem V-Metalloxid-Feldeffekttransistor
DE3334624C2 (https=)
CH615781A5 (https=)
DE2628407A1 (de) Verfahren zum herstellen von vergrabenen dielektrischen isolierungen
DE3150222A1 (de) "verfahren zum herstellen einer halbleitervorrichtung"
DE2745857A1 (de) Verfahren zur herstellung einer halbleiteranordnung
DE2626739A1 (de) Verfahren zur herstellung von monolithisch integrierten halbleiterschaltungen mit durch ionenbombardement hervorgerufenen dielektrischen isolationszonen
DE19837395A1 (de) Verfahren zur Herstellung einer Halbleiter-Isolationsschicht und eines diese Halbleiter-Isolationsschicht enthaltenden Halbleiterbauelements
DE69513469T2 (de) Silizium-auf-Isolator-Substrat und dessen Herstellungsverfahren
DE2420239A1 (de) Verfahren zur herstellung doppelt diffundierter lateraler transistoren
DE2640981C2 (de) Verfahren zur Herstellung von Halbleiteranordnungen durch Ionenimplantation
DE68928951T2 (de) Verfahren zur Herstellung einer integrierten Schaltung mit Bipolartransistoren
DE2409910B2 (de) Verfahren zum Herstellen einer Halbleiteranordnung
DE2705468A1 (de) Verfahren zur herstellung von transistoren durch ionenimplantation
DE3715092C2 (https=)

Legal Events

Date Code Title Description
8110 Request for examination paragraph 44
D2 Grant after examination
8364 No opposition during term of opposition
8328 Change in the person/name/address of the agent

Free format text: HOFFMANN, E., DIPL.-ING., PAT.-ANW., 82166 GRAEFELFING