DE3712178A1 - Halbleitereinrichtung - Google Patents

Halbleitereinrichtung

Info

Publication number
DE3712178A1
DE3712178A1 DE19873712178 DE3712178A DE3712178A1 DE 3712178 A1 DE3712178 A1 DE 3712178A1 DE 19873712178 DE19873712178 DE 19873712178 DE 3712178 A DE3712178 A DE 3712178A DE 3712178 A1 DE3712178 A1 DE 3712178A1
Authority
DE
Germany
Prior art keywords
signal
connection
strip
strips
mos transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
DE19873712178
Other languages
German (de)
English (en)
Other versions
DE3712178C2 (enExample
Inventor
Hideyuki Ozaki
Kazutoshi Hirayama
Kazuyasu Fujishima
Hideto Hidaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Publication of DE3712178A1 publication Critical patent/DE3712178A1/de
Application granted granted Critical
Publication of DE3712178C2 publication Critical patent/DE3712178C2/de
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W44/00—Electrical arrangements for controlling or matching impedance
    • H10W44/20—Electrical arrangements for controlling or matching impedance at high-frequency [HF] or radio frequency [RF]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W44/00—Electrical arrangements for controlling or matching impedance
    • H10W44/601—Capacitive arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/932—Plan-view shape, i.e. in top view
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Wire Bonding (AREA)
  • Dram (AREA)
  • Lead Frames For Integrated Circuits (AREA)
DE19873712178 1986-04-17 1987-04-10 Halbleitereinrichtung Granted DE3712178A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61088716A JP2605687B2 (ja) 1986-04-17 1986-04-17 半導体装置

Publications (2)

Publication Number Publication Date
DE3712178A1 true DE3712178A1 (de) 1987-10-22
DE3712178C2 DE3712178C2 (enExample) 1992-08-27

Family

ID=13950623

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19873712178 Granted DE3712178A1 (de) 1986-04-17 1987-04-10 Halbleitereinrichtung

Country Status (4)

Country Link
US (1) US4808844A (enExample)
JP (1) JP2605687B2 (enExample)
KR (1) KR910000114B1 (enExample)
DE (1) DE3712178A1 (enExample)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3911450A1 (de) * 1988-05-07 1989-11-16 Mitsubishi Electric Corp Integrierte halbleiterschaltung mit waehlbaren betriebsfunktionen
EP0454134A3 (en) * 1990-04-25 1993-05-19 Kabushiki Kaisha Toshiba Semiconductor device
US5347145A (en) * 1990-12-27 1994-09-13 Kabushiki Kaisha Toshiba Pad arrangement for a semiconductor device
US6573593B1 (en) 1996-09-18 2003-06-03 Infineon Technologies Ag Integrated circuit with a housing accommodating the integrated circuit

Families Citing this family (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR900001398B1 (ko) * 1987-11-30 1990-03-09 삼성전자 주식회사 양방성 입출력 셀
KR910003593B1 (ko) * 1987-12-30 1991-06-07 삼성전자 주식회사 고집적도 메모리용 모드 선택회로
US4987325A (en) * 1988-07-13 1991-01-22 Samsung Electronics Co., Ltd. Mode selecting circuit for semiconductor memory device
US4866309A (en) * 1988-07-18 1989-09-12 Western Digital Corporation Multiplexed bus architecture for configuration sensing
US6304987B1 (en) 1995-06-07 2001-10-16 Texas Instruments Incorporated Integrated test circuit
US4987319A (en) * 1988-09-08 1991-01-22 Kawasaki Steel Corporation Programmable input/output circuit and programmable logic device
JP2560805B2 (ja) * 1988-10-06 1996-12-04 三菱電機株式会社 半導体装置
US5161124A (en) * 1988-10-27 1992-11-03 Texas Instruments Incorporated Bond programmable integrated circuit
US4912348A (en) * 1988-12-09 1990-03-27 Idaho Research Foundation Method for designing pass transistor asynchronous sequential circuits
JP3005250B2 (ja) * 1989-06-30 2000-01-31 テキサス インスツルメンツ インコーポレイテツド バスモニター集積回路
US5353250A (en) * 1991-12-09 1994-10-04 Texas Instruments Inc. Pin programmable dram that provides customer option programmability
JP2727921B2 (ja) * 1993-08-13 1998-03-18 日本電気株式会社 半導体集積回路装置
US5557219A (en) * 1994-01-31 1996-09-17 Texas Instruments Incorporated Interface level programmability
US5760643A (en) * 1995-10-31 1998-06-02 Texas Instruments Incorporated Integrated circuit die with selective pad-to-pad bypass of internal circuitry
US5969538A (en) 1996-10-31 1999-10-19 Texas Instruments Incorporated Semiconductor wafer with interconnect between dies for testing and a process of testing
US6408413B1 (en) 1998-02-18 2002-06-18 Texas Instruments Incorporated Hierarchical access of test access ports in embedded core integrated circuits
US6405335B1 (en) 1998-02-25 2002-06-11 Texas Instruments Incorporated Position independent testing of circuits
US7058862B2 (en) * 2000-05-26 2006-06-06 Texas Instruments Incorporated Selecting different 1149.1 TAP domains from update-IR state
JP3334671B2 (ja) * 1999-04-16 2002-10-15 日本電気株式会社 半導体装置及びこれを搭載したモジュール
US6731071B2 (en) * 1999-06-21 2004-05-04 Access Business Group International Llc Inductively powered lamp assembly
US6728915B2 (en) 2000-01-10 2004-04-27 Texas Instruments Incorporated IC with shared scan cells selectively connected in scan path
US6769080B2 (en) 2000-03-09 2004-07-27 Texas Instruments Incorporated Scan circuit low power adapter with counter
JP4313544B2 (ja) * 2002-05-15 2009-08-12 富士通マイクロエレクトロニクス株式会社 半導体集積回路
US7131033B1 (en) 2002-06-21 2006-10-31 Cypress Semiconductor Corp. Substrate configurable JTAG ID scheme
US7818640B1 (en) 2004-10-22 2010-10-19 Cypress Semiconductor Corporation Test system having a master/slave JTAG controller
US20060086940A1 (en) * 2004-10-26 2006-04-27 Jim Wang Package structure of multi-chips light-emitting module

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3218992A1 (de) * 1982-05-19 1983-11-24 Siemens AG, 1000 Berlin und 8000 München Monolithisch integrierter schaltkreis

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56157056A (en) * 1980-05-09 1981-12-04 Fujitsu Ltd Manufacture of read-only memory
US4386284A (en) * 1981-02-06 1983-05-31 Rca Corporation Pulse generating circuit using current source
DE3120163A1 (de) * 1981-05-21 1982-12-09 Deutsche Itt Industries Gmbh, 7800 Freiburg Cmos-auswahlschaltung
JPS5835963A (ja) * 1981-08-28 1983-03-02 Fujitsu Ltd 集積回路装置
JPS6188538A (ja) * 1984-10-05 1986-05-06 Fujitsu Ltd 半導体装置
US4638181A (en) * 1984-11-29 1987-01-20 Rca Corporation Signal source selector
JPS6251231A (ja) * 1985-08-30 1987-03-05 Fujitsu Ltd 半導体集積回路装置
JPH0831789B2 (ja) * 1985-09-04 1996-03-27 沖電気工業株式会社 出力回路

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3218992A1 (de) * 1982-05-19 1983-11-24 Siemens AG, 1000 Berlin und 8000 München Monolithisch integrierter schaltkreis

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
FUJI u.A. A 50muA Stand by 1MW x 1b/256 KW x 4b CMOS DRAM". In: IEEE Int. Sol.-State Circuits Conference, Digest of Techn. Papers, S. 266-267, 1986 *
HORIGUCHI u.a. "A 1Mb DRAM with a Folded Capacitor cell Structure" In: IEEE Int. Sol.-State Circuits Conference, Digest of Techn. Papers, S. 244-245, S. 355,1985 *

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3911450A1 (de) * 1988-05-07 1989-11-16 Mitsubishi Electric Corp Integrierte halbleiterschaltung mit waehlbaren betriebsfunktionen
US4985641A (en) * 1988-05-07 1991-01-15 Mitsubishi Denki Kabushiki Kaisha Semiconductor integrated circuit device having selectable operational functions
EP0454134A3 (en) * 1990-04-25 1993-05-19 Kabushiki Kaisha Toshiba Semiconductor device
US5386127A (en) * 1990-04-25 1995-01-31 Kabushiki Kaisha Toshiba Semiconductor device having groups of pads which receive the same signal
US5347145A (en) * 1990-12-27 1994-09-13 Kabushiki Kaisha Toshiba Pad arrangement for a semiconductor device
US6573593B1 (en) 1996-09-18 2003-06-03 Infineon Technologies Ag Integrated circuit with a housing accommodating the integrated circuit

Also Published As

Publication number Publication date
KR910000114B1 (ko) 1991-01-21
US4808844A (en) 1989-02-28
DE3712178C2 (enExample) 1992-08-27
JPS62244144A (ja) 1987-10-24
JP2605687B2 (ja) 1997-04-30
KR870010628A (ko) 1987-11-30

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Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
D2 Grant after examination
8364 No opposition during term of opposition
8320 Willingness to grant licences declared (paragraph 23)
8328 Change in the person/name/address of the agent

Representative=s name: PRUFER & PARTNER GBR, 81545 MUENCHEN