DE3414772C2 - - Google Patents

Info

Publication number
DE3414772C2
DE3414772C2 DE3414772A DE3414772A DE3414772C2 DE 3414772 C2 DE3414772 C2 DE 3414772C2 DE 3414772 A DE3414772 A DE 3414772A DE 3414772 A DE3414772 A DE 3414772A DE 3414772 C2 DE3414772 C2 DE 3414772C2
Authority
DE
Germany
Prior art keywords
diffusion region
type
substrate
conductivity type
effect transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE3414772A
Other languages
German (de)
English (en)
Other versions
DE3414772A1 (de
Inventor
Takeshi Itami Hyogo Jp Tokuda
Sotoju Toyono Osaka Jp Asai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Publication of DE3414772A1 publication Critical patent/DE3414772A1/de
Application granted granted Critical
Publication of DE3414772C2 publication Critical patent/DE3414772C2/de
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843Source or drain regions of field-effect devices
    • H01L29/0847Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/74Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
    • H01L21/743Making of internal connections, substrate contacts
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0921Means for preventing a bipolar, e.g. thyristor, action between the different transistor regions, e.g. Latchup prevention

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
DE19843414772 1983-04-25 1984-04-18 Komplementaerer feldeffekttransistor Granted DE3414772A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58074274A JPS59198749A (ja) 1983-04-25 1983-04-25 相補形電界効果トランジスタ

Publications (2)

Publication Number Publication Date
DE3414772A1 DE3414772A1 (de) 1984-10-25
DE3414772C2 true DE3414772C2 (da) 1987-10-08

Family

ID=13542371

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19843414772 Granted DE3414772A1 (de) 1983-04-25 1984-04-18 Komplementaerer feldeffekttransistor

Country Status (2)

Country Link
JP (1) JPS59198749A (da)
DE (1) DE3414772A1 (da)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4439131A1 (de) * 1993-11-05 1995-05-11 Mitsubishi Electric Corp Halbleitereinrichtung und Verfahren zur Herstellung derselben
DE4405631C1 (de) * 1994-02-22 1995-07-20 Bosch Gmbh Robert Integriertes Bauelement

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3743930A1 (de) * 1987-12-23 1989-07-06 Siemens Ag Integrierte schaltung mit "latch-up"-schutzschaltung in komplementaerer mos-schaltungstechnik
CN110534512B (zh) * 2019-09-07 2023-02-07 电子科技大学 一种抗闩锁版图结构

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4035826A (en) * 1976-02-23 1977-07-12 Rca Corporation Reduction of parasitic bipolar effects in integrated circuits employing insulated gate field effect transistors via the use of low resistance substrate contacts extending through source region
JPS5931987B2 (ja) * 1977-01-11 1984-08-06 三洋電機株式会社 相補型mosトランジスタ
JPS5843559A (ja) * 1981-09-08 1983-03-14 Mitsubishi Electric Corp 相補型半導体装置

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4439131A1 (de) * 1993-11-05 1995-05-11 Mitsubishi Electric Corp Halbleitereinrichtung und Verfahren zur Herstellung derselben
DE4439131C2 (de) * 1993-11-05 1998-02-19 Mitsubishi Electric Corp Halbleitereinrichtung mit einem Verbindungsbereich und Verfahren zur Herstellung derselben
US6153915A (en) * 1993-11-05 2000-11-28 Mitsubishi Denki Kabushiki Kaisha CMOS semiconductor device
DE4405631C1 (de) * 1994-02-22 1995-07-20 Bosch Gmbh Robert Integriertes Bauelement

Also Published As

Publication number Publication date
JPS59198749A (ja) 1984-11-10
DE3414772A1 (de) 1984-10-25

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Legal Events

Date Code Title Description
OR8 Request for search as to paragraph 43 lit. 1 sentence 1 patent law
8105 Search report available
8110 Request for examination paragraph 44
8125 Change of the main classification

Ipc: H01L 27/10

D2 Grant after examination
8364 No opposition during term of opposition
8320 Willingness to grant licences declared (paragraph 23)
8339 Ceased/non-payment of the annual fee