DE3381732D1 - Packung fuer halbleiterchip. - Google Patents

Packung fuer halbleiterchip.

Info

Publication number
DE3381732D1
DE3381732D1 DE8484900350T DE3381732T DE3381732D1 DE 3381732 D1 DE3381732 D1 DE 3381732D1 DE 8484900350 T DE8484900350 T DE 8484900350T DE 3381732 T DE3381732 T DE 3381732T DE 3381732 D1 DE3381732 D1 DE 3381732D1
Authority
DE
Germany
Prior art keywords
package
semiconductor chip
chip
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8484900350T
Other languages
English (en)
Inventor
Joseph Rainal
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Corp
Original Assignee
Western Electric Co Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Western Electric Co Inc filed Critical Western Electric Co Inc
Application granted granted Critical
Publication of DE3381732D1 publication Critical patent/DE3381732D1/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K7/00—Constructional details common to different types of electric apparatus
    • H05K7/02—Arrangements of circuit components or wiring on supporting structure
    • H05K7/10—Plug-in assemblages of components, e.g. IC sockets
    • H05K7/1053—Plug-in assemblages of components, e.g. IC sockets having interior leads
    • H05K7/1076—Plug-in assemblages of components, e.g. IC sockets having interior leads co-operating by sliding
    • H05K7/1084—Plug-in assemblages of components, e.g. IC sockets having interior leads co-operating by sliding pin grid array package carriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/66—High-frequency adaptations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structure Of Printed Boards (AREA)
DE8484900350T 1982-12-29 1983-12-08 Packung fuer halbleiterchip. Expired - Fee Related DE3381732D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US06/454,197 US4498122A (en) 1982-12-29 1982-12-29 High-speed, high pin-out LSI chip package
PCT/US1983/001927 WO1984002631A1 (en) 1982-12-29 1983-12-08 Semiconductor chip package

Publications (1)

Publication Number Publication Date
DE3381732D1 true DE3381732D1 (de) 1990-08-16

Family

ID=23803685

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8484900350T Expired - Fee Related DE3381732D1 (de) 1982-12-29 1983-12-08 Packung fuer halbleiterchip.

Country Status (7)

Country Link
US (1) US4498122A (de)
EP (1) EP0130207B1 (de)
JP (1) JPS60500111A (de)
CA (1) CA1202732A (de)
DE (1) DE3381732D1 (de)
GB (1) GB2132820B (de)
WO (1) WO1984002631A1 (de)

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JP4341152B2 (ja) * 2000-06-02 2009-10-07 ソニー株式会社 プリント基板の配線構造チェックシステム
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USD927429S1 (en) * 2019-03-15 2021-08-10 Modus Test, Llc Plurality of contact fields for a printed circuit board
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RU2754078C1 (ru) * 2020-07-06 2021-08-26 федеральное государственное бюджетное образовательное учреждение высшего образования «Томский государственный университет систем управления и радиоэлектроники» Способ компоновки многослойных печатных плат для цепей с резервированием
RU2762336C1 (ru) * 2021-03-04 2021-12-20 федеральное государственное бюджетное образовательное учреждение высшего образования «Томский государственный университет систем управления и радиоэлектроники» Способ трассировки двухсторонней печатной платы для цепей с модальным резервированием

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Also Published As

Publication number Publication date
CA1202732A (en) 1986-04-01
US4498122A (en) 1985-02-05
EP0130207A1 (de) 1985-01-09
EP0130207B1 (de) 1990-07-11
GB2132820A (en) 1984-07-11
GB2132820B (en) 1986-10-01
EP0130207A4 (de) 1987-04-28
WO1984002631A1 (en) 1984-07-05
JPH0527985B2 (de) 1993-04-22
JPS60500111A (ja) 1985-01-24
GB8333582D0 (en) 1984-01-25

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8328 Change in the person/name/address of the agent

Free format text: BLUMBACH, KRAMER & PARTNER, 65193 WIESBADEN

8339 Ceased/non-payment of the annual fee