GB1535813A - Multi-layer circuit board - Google Patents
Multi-layer circuit boardInfo
- Publication number
- GB1535813A GB1535813A GB2534476A GB2534476A GB1535813A GB 1535813 A GB1535813 A GB 1535813A GB 2534476 A GB2534476 A GB 2534476A GB 2534476 A GB2534476 A GB 2534476A GB 1535813 A GB1535813 A GB 1535813A
- Authority
- GB
- United Kingdom
- Prior art keywords
- circuit
- patterns
- degree
- artwork
- masters
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0002—Apparatus or processes for manufacturing printed circuits for manufacturing artworks for printed circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0286—Programmable, customizable or modifiable circuits
- H05K1/0287—Programmable, customizable or modifiable circuits having an universal lay-out, e.g. pad or land grid patterns or mesh patterns
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0286—Programmable, customizable or modifiable circuits
- H05K1/029—Programmable, customizable or modifiable circuits having a programmable lay-out, i.e. adapted for choosing between a few possibilities
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0286—Programmable, customizable or modifiable circuits
- H05K1/0287—Programmable, customizable or modifiable circuits having an universal lay-out, e.g. pad or land grid patterns or mesh patterns
- H05K1/0289—Programmable, customizable or modifiable circuits having an universal lay-out, e.g. pad or land grid patterns or mesh patterns having a matrix lay-out, i.e. having selectively interconnectable sets of X-conductors and Y-conductors in different planes
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
- H05K1/0298—Multilayer circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
- H05K2201/09945—Universal aspects, e.g. universal inner layers or via grid, or anisotropic interposer
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/05—Patterning and lithography; Masks; Details of resist
- H05K2203/0548—Masks
- H05K2203/056—Using an artwork, i.e. a photomask for exposing photosensitive layers
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
- H05K3/4641—Manufacturing multilayer circuits by laminating two or more circuit boards having integrally laminated metal sheets or special power cores
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Structure Of Printed Boards (AREA)
Abstract
1535813 Masters for printed circuits N C R CORP 18 June 1976 [3 July 1975] 25344/76 Heading G2X [Also in Division H1] In a multi-layer printed circuit board 1 with at least one internal circuit layer, desired patterns of outer circuit layers 5, 10, Fig. 2, are produced from artwork masters generated from layout patterns initially made to a first degree of layout precision, by altering these patterns, the alterations being effected to a second degree of layout precision which is less than the first. As shown, the initial circuit patterns of the outer layers 5, 10 to the first degree of precision include mutually perpendicular sets of parallel conductor runs 38, 54, Fig. 13, interconnecting pads, and signal pads 42, 62, Fig. 2 shorter conductor runs 44-46 and 64-66 between the pads and the main runs 38, 54 are produced to the second degree of accuracy resulting in the particular configuration desired for the intended circuit use. Connections through the board from one circuit pattern 5 to the other 10 are made by plated through-holes 14, Fig. 2. As shown in Fig. 13, initial artwork layouts for the circuits 5, 10, e.g. produced on an automatic X-Y plotter, are superposed and the necessary alterations e.g. traces 45, 64 are marked on a transparent sheet 110 laid over the patterns. The marked sheet 110 is then used as an underlay and the alterations are transferred to the artwork layouts to produce the masters corresponding to circuit layers 5, 10, Fig. 14, 15 (not shown). One of the internal circuit patterns 6-9, Fig. 2, e.g. a ground plane circuit 8, is used to ensure correct dimensional control in the photoreduction of the completed artwork masters. The plated through holes 14 are made from a drilling template and the components are then installed on the board.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US59334175A | 1975-07-03 | 1975-07-03 |
Publications (1)
Publication Number | Publication Date |
---|---|
GB1535813A true GB1535813A (en) | 1978-12-13 |
Family
ID=24374344
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB2534476A Expired GB1535813A (en) | 1975-07-03 | 1976-06-18 | Multi-layer circuit board |
Country Status (5)
Country | Link |
---|---|
JP (1) | JPS526974A (en) |
CA (1) | CA1055164A (en) |
DE (1) | DE2629303C3 (en) |
FR (1) | FR2316833A1 (en) |
GB (1) | GB1535813A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2132820A (en) * | 1982-12-29 | 1984-07-11 | Western Electric Co | Integrated circuit chip package |
GB2227124A (en) * | 1988-12-09 | 1990-07-18 | Hitachi Chemical Co Ltd | Circuit board and process for producing the same |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE3020196C2 (en) * | 1980-05-28 | 1982-05-06 | Ruwel-Werke Spezialfabrik für Leiterplatten GmbH, 4170 Geldern | Multilevel printed circuit board and process for its manufacture |
US4894689A (en) * | 1984-12-28 | 1990-01-16 | American Telephone And Telegraph Company, At&T Bell Laboratories | Transferred electron device |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE1919421C3 (en) * | 1969-04-17 | 1975-03-13 | Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt | Multilayer circuit board |
GB1310880A (en) * | 1969-06-13 | 1973-03-21 | Microponent Dev Ltd | Multi-layer printed circuit board assemblies |
DE2059425A1 (en) * | 1970-12-02 | 1972-06-22 | Siemens Ag | Partial structure of printed multilayer circuits |
-
1976
- 1976-06-18 GB GB2534476A patent/GB1535813A/en not_active Expired
- 1976-06-21 CA CA255,356A patent/CA1055164A/en not_active Expired
- 1976-06-30 DE DE19762629303 patent/DE2629303C3/en not_active Expired
- 1976-07-02 FR FR7620215A patent/FR2316833A1/en active Granted
- 1976-07-02 JP JP7880576A patent/JPS526974A/en active Pending
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2132820A (en) * | 1982-12-29 | 1984-07-11 | Western Electric Co | Integrated circuit chip package |
GB2227124A (en) * | 1988-12-09 | 1990-07-18 | Hitachi Chemical Co Ltd | Circuit board and process for producing the same |
GB2227124B (en) * | 1988-12-09 | 1993-05-26 | Hitachi Chemical Co Ltd | Wiring board and process for producing the same |
US5243144A (en) * | 1988-12-09 | 1993-09-07 | Hitachi Chemical Company, Ltd. | Wiring board and process for producing the same |
Also Published As
Publication number | Publication date |
---|---|
CA1055164A (en) | 1979-05-22 |
FR2316833A1 (en) | 1977-01-28 |
FR2316833B1 (en) | 1982-01-29 |
DE2629303C3 (en) | 1981-03-26 |
JPS526974A (en) | 1977-01-19 |
DE2629303B2 (en) | 1980-07-17 |
DE2629303A1 (en) | 1977-01-20 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
GB1111088A (en) | Improvements in or relating to multi-layer circuit boards | |
GB1534492A (en) | Precision transducer for position measurements and method of manufacture | |
US2942973A (en) | Method of making drawings | |
GB1535813A (en) | Multi-layer circuit board | |
US4361634A (en) | Artwork master for production of multilayer circuit board | |
US3385702A (en) | Photomechanical method of making metallic patterns | |
US3508919A (en) | Master artwork technique for producing printed wiring boards | |
US3594168A (en) | Method for fabricating photographic artwork for printed circuits | |
GB1436776A (en) | Printed circuits | |
ES455373A1 (en) | Multilayer printed wiring board | |
US3723211A (en) | Preparation of layout sheets for printed wiring | |
JPS52111660A (en) | Method of producing multilayer printed circuit board internal layer circuit pattern | |
JPS5225265A (en) | Method of measuring accuracy of pattern on multilayered printed wiring board | |
SU832793A1 (en) | Method of making holes in printed-circuit boards | |
SU809668A1 (en) | Multilayer printed circuit board | |
GB1367601A (en) | Circuit systems | |
GB1498861A (en) | Method for the manufacture of masters for printed circuit | |
SU849567A1 (en) | Method of making mounting holes in printed-circuit boards | |
SU549899A1 (en) | PCB pattern making apparatus | |
JPS52145773A (en) | Method of producing multilayer printed circuit board | |
JPS5296356A (en) | Method of producing multilayer printed circuit board | |
JPH02295183A (en) | Printed wiring board | |
JPS6464292A (en) | Manufacture of printed board | |
JPH0135493Y2 (en) | ||
JPS6219969A (en) | Method of preparing printed board library by cad |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PS | Patent sealed | ||
PCNP | Patent ceased through non-payment of renewal fee |