JPS6219969A - Method of preparing printed board library by cad - Google Patents
Method of preparing printed board library by cadInfo
- Publication number
- JPS6219969A JPS6219969A JP60159087A JP15908785A JPS6219969A JP S6219969 A JPS6219969 A JP S6219969A JP 60159087 A JP60159087 A JP 60159087A JP 15908785 A JP15908785 A JP 15908785A JP S6219969 A JPS6219969 A JP S6219969A
- Authority
- JP
- Japan
- Prior art keywords
- cad
- laminated
- land
- printed board
- board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
Description
【発明の詳細な説明】
〔概要〕
本発明は所謂ＣＡＤ／ＣＡＭ （Ｃｏｍｐｕｔｏｒ
Ａｉｄｅｄ Ｄｅｓｉｇｎ ／Ｃｏｍｐｕｔｏｒ Ａｉ
ｄｅｄ Ｍａｎｕｆａｃｔｕｒｉｎｇ）方式によるプリ
ント基板搭載部品の配置やその回路パターンの編集処理
をなす手法に係り、特に、積層基板数に無関係に部品装
着のランド定義を与える手法を提示している。[Detailed Description of the Invention] [Summary] The present invention applies to so-called CAD/CAM (Computer
Aided Design /Computer AI
This paper relates to a method for arranging components mounted on a printed circuit board and editing their circuit patterns using the ED Manufacturing method, and particularly presents a method for providing land definitions for mounting components regardless of the number of laminated boards.
本発明は基板回路設計に係るＣＡＤによるプリント基板
ライブラリ作成法に関する。The present invention relates to a printed circuit board library creation method using CAD related to circuit board circuit design.
ＣＡＤによる基板回路データの自動パターン化処理は、
従来の手作業図面に比べて正確で美しい図面がＸＹブロ
ックに自動的に出力されること、然もプロッタ出力の図
面は配線パターン寸法値の誤記入に原因する設計ミスが
皆無となること等の利点があることから、設計部門も含
む製造現場の生産性向上を実現する道具として着目され
ている。Automatic patterning processing of board circuit data using CAD is
Compared to conventional manual drawings, more accurate and beautiful drawings are automatically output to the XY block, and plotter output drawings are completely free from design errors caused by incorrect entry of wiring pattern dimensions. Because of its advantages, it is attracting attention as a tool to improve productivity at manufacturing sites, including design departments.
積層プリント板表面に実装するＳＭＤ （Ｓｕｒｆａｃ
ｓ品の取付は方法を示す基板一部分の正面図（イ）並び
に側面図（ロ）である。SMD (Surfac) mounted on the surface of a laminated printed board
A front view (a) and a side view (b) of a part of the board show how to install the S product.
正面図において、Ｒは抵抗、又、Ｄは基板１０の表面に
予形成された部品取付はランド部のパッドである。該パ
ッドＤは部品取付は面にだけあればよく他の層には不要
である。In the front view, R is a resistor, and D is a pad at a land portion for mounting components preformed on the surface of the substrate 10. The pad D is only necessary for mounting components on the surface and is not required on other layers.
このような積層構成プリント基板に対して形成された部
品実装用ランドＥは、従来衣の如きランド定義がされる
。A component mounting land E formed on such a laminated printed circuit board is defined like a conventional land.
ランドＥ 孔 なし
積層の表面層のみ パッドＤ
積層の他の層 パッドＦ
但しパッドＦはパッド無しを意味する。−前記ＳＭＤ部
品によらないスルーホール形成の部品取付はランドＡ
（図示せず）を定義する時は。Land E Only the surface layer of the laminated layer without holes Pad D Other layers of the laminated layer Pad F However, Pad F means no pad. - Land A is used for mounting parts with through holes that are not based on the SMD parts.
(not shown) when defining.
ランドＡ 孔 あり 積層の全層 パッドＤ としていた。Land A with hole All layers of lamination Pad D It was.
このように積層基板に実装する部品取付は方法の変更に
伴いランド定義を変えているが、しかし。In this way, land definitions are changing due to changes in the mounting method for components mounted on laminated boards.
従来のライブラリ定義によれば積層基板１０の層構成が
変わる度に層構成に合わせて再定義せねばならずプログ
ラム作成の観点から甚だ不都合である。According to the conventional library definition, each time the layer configuration of the laminated substrate 10 changes, the definition must be redefined according to the layer configuration, which is extremely inconvenient from the viewpoint of program creation.
積層構成プリント基板の表面に部品装着をなすためのラ
ンド定義を、積層基板数に無関係に行ないうる本発明に
よるＣＡＤによるプリント基板ライブラリ作成法とする
ことにより前記の問題点は解決される。The above problems are solved by the method of creating a printed circuit board library using CAD according to the present invention, which allows land definition for mounting components on the surface of a laminated printed circuit board, regardless of the number of laminated circuit boards.
積層プリント基板の積層基板数に無関係に部品装着ラン
ド部の定義がされることから、 ＣＡＤ設計の効率化
が図られることとなる。Since component mounting lands are defined regardless of the number of laminated printed circuit boards, CAD design becomes more efficient.
以下１本発明の実施例を示す次表を参照して本発明の詳
細な説明する。The present invention will now be described in detail with reference to the following table showing one example of the present invention.
表中＋Ｌｌ ＋Ｌ２ ＋Ｌ４−・・・−・−Ｌｎの記号
は２表面プリント基板をＬｌとして下方に積層される層
基板数である（ ＳＭＤ部品の基板取付は図参照）。The symbols +Ll +L2 +L4-...--Ln in the table indicate the number of layered boards stacked below, with the two-surface printed board as Ll (see the figure for board mounting of SMD parts).
表中には六層構成までの本発明と従来手法それぞれの積
層基板数に応じてなすランド定義が示されている。In the table, land definitions are shown according to the number of laminated boards of the present invention and the conventional method up to a six-layer structure.
表から明らかな様に本発明の新手法によれば。As is clear from the table, according to the new method of the present invention.
層構成に無関係に一回の定義によりすべての積層基板に
適用されることとなり、従ってライブラリ定義が非常に
簡単且つ容易に行える利点がある。A single definition applies to all laminated substrates regardless of the layer configuration, so there is an advantage that library definition can be performed very simply and easily.
尚、前記実施例における部品実装面はＬ１基板であるが
、該実装面はＬｎ側にも設定可能であり。Although the component mounting surface in the above embodiment is the L1 board, the mounting surface can also be set on the Ln side.
この場合１次の様にすることにより同様に実現出来る。In this case, it can be similarly realized by doing it in a first-order manner.
形状
Ｌｌ 〜Ｌｎ−１パッドＦ
Ｌｎ パッドＤ
〔発明の効果〕
前記実施例から明らかなように本発明のプリント基板ラ
イブラリ作成法によれば、従来２層構成に合わせてその
都度再定義していたランド指定の面倒な手順が解消され
るので例えばＣＡＤプログラム工数が短縮化される等の
利点がある。Shape Ll ~ Ln-1 Pad F Ln Pad D [Effects of the Invention] As is clear from the above embodiments, according to the method of creating a printed circuit board library of the present invention, conventionally, the shape was redefined each time according to the two-layer configuration. Since the troublesome procedure of land designation is eliminated, there is an advantage that, for example, the man-hours for CAD programming can be shortened.
／ρ 輩１図/ρ Senior 1 figure
Claims (1)
ランド定義を、積層基板数に無関係にすることを特徴と
するＣＡＤによるプリント基板ライブラリ作成法。A printed circuit board library creation method using CAD, characterized in that land definition for mounting components on the surface of a laminated printed circuit board is made independent of the number of laminated circuit boards.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60159087A JPS6219969A (en) | 1985-07-18 | 1985-07-18 | Method of preparing printed board library by cad |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60159087A JPS6219969A (en) | 1985-07-18 | 1985-07-18 | Method of preparing printed board library by cad |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6219969A true JPS6219969A (en) | 1987-01-28 |
Family
ID=15685947
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60159087A Pending JPS6219969A (en) | 1985-07-18 | 1985-07-18 | Method of preparing printed board library by cad |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6219969A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63291496A (en) * | 1987-05-25 | 1988-11-29 | Ibiden Co Ltd | Removal of unnecessary land in multilayered substrate |
| JPH03107118U (en) * | 1989-11-28 | 1991-11-05 |
-
1985
- 1985-07-18 JP JP60159087A patent/JPS6219969A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63291496A (en) * | 1987-05-25 | 1988-11-29 | Ibiden Co Ltd | Removal of unnecessary land in multilayered substrate |
| JPH0550028B2 (en) * | 1987-05-25 | 1993-07-27 | Ibiden Co Ltd | |
| JPH03107118U (en) * | 1989-11-28 | 1991-11-05 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP3230953B2 (en) | Multilayer thin film wiring board | |
| JPS6219969A (en) | Method of preparing printed board library by cad | |
| JPH0369191A (en) | Multi-layer printed-circuit board with built-in electronic parts | |
| JPH04340795A (en) | Printed circuit board | |
| JPS6038878B2 (en) | Pattern connection structure of multilayer printed wiring board | |
| JPH053160B2 (en) | ||
| JP3181353B2 (en) | Multi-layer printed wiring board design CAD system | |
| JP3531858B2 (en) | Multilayer printed circuit board | |
| JPH11307890A (en) | Printed wiring board | |
| JPS61107788A (en) | Universal material for printed wiring board and manufacture of printed circuit board using the same | |
| US20030102159A1 (en) | Optimum power and ground bump pad and bump patterns for flip chip packaging | |
| JPH01200690A (en) | Printed wiring board | |
| JPH04346492A (en) | Manufacture of hybrid integrated circuit board | |
| JPH01209794A (en) | Manufacture of multilayer printed circuit substrate | |
| JPS6348143Y2 (en) | ||
| JP2846759B2 (en) | Multilayer printed wiring board | |
| JP3796815B2 (en) | Inner layer substrate and design device thereof | |
| GB1535813A (en) | Multi-layer circuit board | |
| JPH0226399B2 (en) | ||
| JPH06169154A (en) | Printed wiring board | |
| JP3297611B2 (en) | Manufacturing panel design system | |
| JPH04162593A (en) | Drilling through multilayer printed wiring board and formation of land pattern | |
| JPH0357645A (en) | Preparation of multilayer printed wiring board | |
| JPH08213726A (en) | Printed board | |
| JPS6371598U (en) |