JPH0226399B2 - - Google Patents
Info
- Publication number
- JPH0226399B2 JPH0226399B2 JP14483984A JP14483984A JPH0226399B2 JP H0226399 B2 JPH0226399 B2 JP H0226399B2 JP 14483984 A JP14483984 A JP 14483984A JP 14483984 A JP14483984 A JP 14483984A JP H0226399 B2 JPH0226399 B2 JP H0226399B2
- Authority
- JP
- Japan
- Prior art keywords
- pattern
- manufacturing
- pattern wiring
- stud
- hole
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000004519 manufacturing process Methods 0.000 claims description 18
- 238000000034 method Methods 0.000 claims description 15
- 239000000758 substrate Substances 0.000 claims description 10
- 239000000853 adhesive Substances 0.000 claims description 9
- 230000001070 adhesive effect Effects 0.000 claims description 9
- 238000010030 laminating Methods 0.000 claims description 3
- 239000000463 material Substances 0.000 claims description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 10
- 229910052802 copper Inorganic materials 0.000 description 10
- 239000010949 copper Substances 0.000 description 10
- 238000007747 plating Methods 0.000 description 8
- 238000005530 etching Methods 0.000 description 5
- 239000004020 conductor Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000003475 lamination Methods 0.000 description 3
- 239000011347 resin Substances 0.000 description 3
- 229920005989 resin Polymers 0.000 description 3
- 238000005253 cladding Methods 0.000 description 2
- 238000007650 screen-printing Methods 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 239000003973 paint Substances 0.000 description 1
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は片面のパターン配線を有するプリント
基板を積層することにより形成される多層プリン
ト板の製造方法に係り、特に、各積層間のパター
ン配線の接続が積層工程において容易に行なえる
多層プリント板の製造方法に関する。Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a method for manufacturing a multilayer printed board formed by laminating printed circuit boards having pattern wiring on one side, and in particular, to The present invention relates to a method for manufacturing a multilayer printed board in which connections can be easily made in a lamination process.
各種電子機器の構成に広く使用されるプリント
板は、その大小を問わず一般的に銅張りした絶縁
基板が使用され、エツチング・レジストを塗布し
てパターン焼付を行ない、不要の部分を除去する
化学処理によつてパターン配線が形成されること
により製造される。 Printed boards, which are widely used in the construction of various electronic devices, are generally made of copper-clad insulating boards, regardless of their size, and are coated with a chemical etching resist to print the pattern and remove unnecessary parts. It is manufactured by forming pattern wiring through processing.
近年、このようなプリント板は高密度実装を図
るため、前述のパターン配線の上面に、更に絶縁
層とパターン配線層を積層するビルドアツプ法な
どによりパターン配線の多層化された多層プリン
ト板の製造が行なわれるようになつた。 In recent years, in order to achieve high-density mounting of such printed boards, it has become possible to manufacture multilayer printed boards with multiple layers of pattern wiring using the build-up method, which further laminates an insulating layer and a pattern wiring layer on top of the pattern wiring described above. It began to be practiced.
しかし、このようなビルドアツプ法によつて製
造された多層プリント板は高価になり易く、特に
利用度の高い積層数の2〜3層の多層プリント板
の安価な製造法が要望されている。 However, multilayer printed boards manufactured by such a build-up method tend to be expensive, and there is a need for an inexpensive manufacturing method for multilayer printed boards with a particularly high number of laminated layers of 2 to 3 layers.
第2図のa,b,c,d,e,f図は従来、最
も広く用いられている多層プリント板の製造方法
の概略工程を工程順に示した側断面図である。
Figures a, b, c, d, e, and f of FIG. 2 are side sectional views showing the schematic steps of the conventionally most widely used method for manufacturing a multilayer printed board in order of process.
a図に示すように絶縁基板1,2,3の間にパ
ターン配線4,5が形成され、絶縁基板1,3の
それぞれの表面に銅張り6が施されたプリント基
板を用い、先づ、スルホールを設ける所定箇所に
はb図に示すように貫通孔7の加工が行なわれ
る。 As shown in Fig. a, pattern wiring 4, 5 is formed between insulating substrates 1, 2, 3, using a printed circuit board with copper coating 6 applied to the surface of each insulating substrate 1, 3, first, A through hole 7 is machined at a predetermined location where a through hole is to be provided, as shown in Figure b.
次に、c図に示すように銅張り6と貫通孔7の
内周とに銅メツキ層8を形成し、更に、d図に示
すように銅メツキ層8の表面の全面にエツチン
グ・レジスト9を施し、パターン焼付を行う。 Next, as shown in figure c, a copper plating layer 8 is formed on the copper cladding 6 and the inner periphery of the through hole 7, and furthermore, as shown in figure d, an etching resist 9 is applied to the entire surface of the copper plating layer 8. and print the pattern.
パターン焼付後、現像処理してパターン以外の
銅メツキ層8および銅張り6を除去することによ
りe図に示すように形成される。最後に化学的に
エツチング・レジスト8を除去することによりf
図に示すパターン配線11とランドを有し、各層
間のパターン配線4,5を接続したスルホール1
0とを形成した多層プリント板が得られる。 After the pattern is baked, development is performed to remove the copper plating layer 8 and the copper cladding 6 other than the pattern, thereby forming the pattern as shown in Fig. e. Finally, by chemically removing the etching resist 8, f
Through-hole 1 has pattern wiring 11 and lands shown in the figure, and connects pattern wiring 4 and 5 between each layer.
A multilayer printed board is obtained in which 0 is formed.
〔発明が解決しようとする問題点〕
このような多層プリント板の製造ではスルホー
ル10用の貫通孔7を加工する場合、パターン配
線が切断されないよう各層に形成されたパターン
配線4,5の位置は互いに正確に位置合わせされ
るよう高精度の積層技術によつて積層しなければ
ならず、更に、積層後、銅メツキ層8の形成およ
びエツチング処理加工を行うため、コストアツプ
となる問題を有していた。[Problems to be Solved by the Invention] In manufacturing such a multilayer printed board, when processing the through holes 7 for the through holes 10, the positions of the pattern wirings 4 and 5 formed in each layer are adjusted so that the pattern wirings are not cut. The layers must be laminated using a high-precision layering technique so that they are accurately aligned with each other, and furthermore, the copper plating layer 8 must be formed and etched after lamination, which increases costs. Ta.
前述の問題点は、かゝる絶縁基板を介して対向
される一方のパターン配線の所定箇所には導電材
によるスタツドを形成し、他方のパターン配線に
は該スタツドの挿入される貫通孔を形成し、該貫
通孔に挿入された該スタツドの先端部には導電性
接着剤がスクリーン印刷されて成る本発明による
製造方法により解決される。
The problem mentioned above is that studs made of a conductive material are formed at predetermined locations on one of the pattern wirings facing each other with an insulating substrate interposed therebetween, and a through hole into which the stud is inserted is formed in the other pattern wiring. However, this problem is solved by the manufacturing method of the present invention, in which a conductive adhesive is screen printed on the tip of the stud inserted into the through hole.
即ち、パターン配線に設けられたスタツドを他
のパターン配線に設けられた貫通孔に挿入するこ
とによつて相互接続の正しい位置決めが行なわ
れ、該スタツド先端の導電性接着剤によつて、各
層間のパターン配線の確実な相互接続が行なわれ
る。
That is, correct positioning of interconnection is achieved by inserting a stud provided in one pattern wiring into a through hole provided in another pattern wiring, and the conductive adhesive at the tip of the stud connects each layer. Reliable interconnection of pattern wiring is achieved.
したがつて、従来のような銅メツキ層の形成お
よびエツチング処理工程によつて形成されるスル
ホールを設けることなく、各層間のパターン配線
相互接続が行なえる。 Therefore, pattern wiring interconnection between each layer can be achieved without providing through holes formed by the conventional process of forming a copper plating layer and etching process.
以下本発明を第1図の一実施例によつて詳細に
説明する。図において、a図は断面図、b1,b
2,b3,c1,c2,d1,d2図は製造方法
の工程を工程順に示した断面図である。全図を通
じ同一符号は同一対象物を示す。
The present invention will be explained in detail below with reference to an embodiment shown in FIG. In the figure, a is a cross-sectional view, b1, b
Figures 2, b3, c1, c2, d1, and d2 are cross-sectional views showing the steps of the manufacturing method in order of process. The same reference numerals indicate the same objects throughout the figures.
a図に示すように表面を樹脂層24により平滑
化された絶縁基板22のパターン配線23には導
電材のスタツド25が固着され、一方、絶縁基板
27のパターン配線28には貫通孔29を設け、
貫通孔29にスタツド25を挿入して積載する。 As shown in Fig. a, studs 25 of a conductive material are fixed to the pattern wiring 23 of the insulating substrate 22 whose surface is smoothed with a resin layer 24, while through holes 29 are provided in the pattern wiring 28 of the insulating substrate 27. ,
The studs 25 are inserted into the through holes 29 and loaded.
このように積載した基板27は基板22と接着
剤30によつて相互に固着し、更に、スタツド2
5の先端部に塗布された導電性接着剤31によつ
てパターン配線23,28の相互接続が行なわれ
る。 The substrates 27 loaded in this way are fixed to each other by the substrate 22 and the adhesive 30, and the studs 2
The pattern wirings 23 and 28 are interconnected by a conductive adhesive 31 applied to the tip of the wiring pattern 5 .
このような構成は次の製造工程順序によつて製
造することができる。先づ、パターン配線23が
形成されたb1図に示すアルミ材などの放熱板2
1を有する絶縁基板22にはb2図に示すように
パターン配線23と同面になる樹脂層24をスク
リーン印刷により形成する。 Such a configuration can be manufactured by the following manufacturing process sequence. First, heat dissipation plate 2 made of aluminum material or the like shown in figure b1 on which pattern wiring 23 is formed.
1, a resin layer 24 is formed on the same surface as the pattern wiring 23 by screen printing, as shown in figure b2.
次に、パターン配線23の所定箇所には導電材
によつて形成されたスタツド25をb3図に示す
ように固着し、プリント板20を製造する。 Next, studs 25 made of a conductive material are fixed to predetermined locations of the pattern wiring 23 as shown in Figure b3, thereby manufacturing the printed board 20.
一方、c1図に示すフイルム状の絶縁シート2
7に設けられたパターン配線28にはc2図に示
すように貫通孔29を加工したプリント板26を
製造する。 On the other hand, a film-like insulating sheet 2 shown in Fig. c1
A printed board 26 is manufactured in which a through hole 29 is formed in the patterned wiring 28 provided in the wiring pattern 7 as shown in Fig. c2.
このプリント板20には26がスタツド25を
貫通孔29に挿入することでd1図に示すように
積載され、接着剤30によつて固着し、更に、ス
タツド25の先端部にはd2図に示すように導電
性接着剤31をスクリーン印刷によつて固着す
る。 26 is loaded onto this printed board 20 by inserting the stud 25 into the through hole 29 as shown in Figure d1, and is fixed with adhesive 30. Furthermore, the tip of the stud 25 is attached as shown in Figure d2. The conductive adhesive 31 is fixed by screen printing.
したがつて、このように製造することで、従来
のようなスルホール10を設けることなく、積層
間のパターン配線23と28とが電気的に接続さ
れた多層プリント板を製造することができる。 Therefore, by manufacturing in this way, it is possible to manufacture a multilayer printed board in which the pattern wirings 23 and 28 between the laminated layers are electrically connected without providing the through holes 10 as in the conventional case.
以上説明したように本発明は夫々片面にパター
ン配線を有する複数個のプリント板をスタツドと
貫通孔によつて位置合わせして積層し、パターン
間の電気接続を導電性塗料によつて行うことによ
り、従来のような高精度の位置合せは不要となり
積層後の銅メツキ層の形成およびエツチング処理
の工程も不要となり、安易な製造設備で安価な多
層プリント板が得られる経済的効果が大である。
As explained above, the present invention involves laminating a plurality of printed boards each having pattern wiring on one side by aligning them with studs and through holes, and making electrical connections between the patterns using conductive paint. , there is no need for high-precision alignment as in the past, and there is no need for the formation of a copper plating layer after lamination or the etching process, and there is a great economic effect in that inexpensive multilayer printed boards can be obtained with simple manufacturing equipment. .
第1図は本発明による多層プリント板の製造方
法の一実施例を説明したa図は断面図、b1,b
2,b3,c1,c2,d1,d2図は製造工程
を示す断面図、第2図は従来の多層プリント板の
製造工程を示すa,b,c,d,e,f図は断面
図を示す。
図中において、1,2,3,22は絶縁基板、
4,5はパターン層、6は銅張り、7,29は貫
通孔、8はメツキ層、9はエツチング・レジス
ト、10はスルホール、11,23,28はパタ
ーン配線、20,26はプリント板、21は放熱
板、27は絶縁シート、24は樹脂層、25はス
タツド、30は接着剤、31は導電性接着剤を示
す。
Figure 1 illustrates an embodiment of the method for manufacturing a multilayer printed board according to the present invention. Figure a is a sectional view, b1, b
Figures 2, b3, c1, c2, d1, and d2 are cross-sectional views showing the manufacturing process, and Figures a, b, c, d, e, and f are cross-sectional views showing the manufacturing process of a conventional multilayer printed board. show. In the figure, 1, 2, 3, 22 are insulating substrates,
4 and 5 are pattern layers, 6 is copper plating, 7 and 29 are through holes, 8 is a plating layer, 9 is an etching resist, 10 is a through hole, 11, 23 and 28 are pattern wirings, 20 and 26 are printed boards, 21 is a heat sink, 27 is an insulating sheet, 24 is a resin layer, 25 is a stud, 30 is an adhesive, and 31 is a conductive adhesive.
Claims (1)
のプリント基板が積層されて形成された多層プリ
ント板の製造方法であつて、前記絶縁基板を介し
て対向される一方のパターン配線の所定箇所には
導電材によるスタツドを形成し、他方のパターン
配線には該スタツドの挿入される貫通孔を形成
し、該貫通孔に挿入された該スタツドの先端部に
は導電性接着剤がスクリーン印刷されて成ること
を特徴とする多層プリント板の製造方法。1. A method for manufacturing a multilayer printed board formed by laminating a plurality of printed circuit boards having pattern wiring on one side of an insulating substrate, wherein a predetermined portion of one of the pattern wirings facing through the insulating substrate is conductive. A stud is formed of a material, a through hole into which the stud is inserted is formed in the other pattern wiring, and a conductive adhesive is screen printed on the tip of the stud inserted into the through hole. A method for manufacturing a multilayer printed board characterized by:
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14483984A JPS6124298A (en) | 1984-07-12 | 1984-07-12 | Method of producing multilayer printed board |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14483984A JPS6124298A (en) | 1984-07-12 | 1984-07-12 | Method of producing multilayer printed board |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6124298A JPS6124298A (en) | 1986-02-01 |
JPH0226399B2 true JPH0226399B2 (en) | 1990-06-08 |
Family
ID=15371629
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP14483984A Granted JPS6124298A (en) | 1984-07-12 | 1984-07-12 | Method of producing multilayer printed board |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6124298A (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0534138Y2 (en) * | 1987-04-17 | 1993-08-30 | ||
JP3057924B2 (en) * | 1992-09-22 | 2000-07-04 | 松下電器産業株式会社 | Double-sided printed circuit board and method of manufacturing the same |
-
1984
- 1984-07-12 JP JP14483984A patent/JPS6124298A/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS6124298A (en) | 1986-02-01 |
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