JPS6038878B2 - Pattern connection structure of multilayer printed wiring board - Google Patents

Pattern connection structure of multilayer printed wiring board

Info

Publication number
JPS6038878B2
JPS6038878B2 JP52018922A JP1892277A JPS6038878B2 JP S6038878 B2 JPS6038878 B2 JP S6038878B2 JP 52018922 A JP52018922 A JP 52018922A JP 1892277 A JP1892277 A JP 1892277A JP S6038878 B2 JPS6038878 B2 JP S6038878B2
Authority
JP
Japan
Prior art keywords
printed wiring
wiring board
layer pattern
inner layer
multilayer printed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP52018922A
Other languages
Japanese (ja)
Other versions
JPS53109173A (en
Inventor
茂 坂本
和幸 吉田
由紀夫 宮村
英俊 小野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP52018922A priority Critical patent/JPS6038878B2/en
Publication of JPS53109173A publication Critical patent/JPS53109173A/en
Publication of JPS6038878B2 publication Critical patent/JPS6038878B2/en
Expired legal-status Critical Current

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  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)

Description

【発明の詳細な説明】 この発明は多層印刷配線板の半製品化を可能にする多層
印刷配線板のパターン接続構造に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a pattern connection structure for a multilayer printed wiring board that enables semi-finished production of the multilayer printed wiring board.

従来、多層印刷配線板の内層パターンと、実装された電
子部品端子との接続は、電子部品端子の挿入されたスル
ホールメッキ穴、即ち内壁にメッキ層が形成されたスル
ーホールを通じて第1図のように行なわれていた。
Conventionally, the inner layer pattern of a multilayer printed wiring board and the mounted electronic component terminal are connected through a through-hole plating hole into which the electronic component terminal is inserted, that is, a through hole with a plating layer formed on the inner wall, as shown in Figure 1. It was carried out in

第1図において、1は従来の製造方法による4層印刷配
線板、2は1/4層外層パターン、3は2/小宮内層パ
ターン、4は3/4層内層パターン、5は4/4層外層
パターン、6は電子部品端子が挿入されたスルホールメ
ツキ穴、7はICや複合抵抗等の電子部品、8は電子部
品端子である。第1図において内層パターンと電子部品
端子との接続は、電子部品端子8の挿入されたスルホー
ルメッキ穴6によって接続されている。
In FIG. 1, 1 is a 4-layer printed wiring board manufactured by a conventional manufacturing method, 2 is a 1/4 layer outer layer pattern, 3 is a 2/Komiya inner layer pattern, 4 is a 3/4 layer inner layer pattern, and 5 is a 4/4 layer pattern. The outer layer pattern, 6 is a through-hole plating hole into which an electronic component terminal is inserted, 7 is an electronic component such as an IC or a composite resistor, and 8 is an electronic component terminal. In FIG. 1, the inner layer pattern and the electronic component terminals are connected by through-hole plating holes 6 into which electronic component terminals 8 are inserted.

第2図は、多層印刷配線板が良く使われる、電子部品7
が多数実装されれた印刷回路組立板の一例を示したもの
である。
Figure 2 shows an electronic component 7 in which multilayer printed wiring boards are often used.
This figure shows an example of a printed circuit assembly board on which a large number of are mounted.

第2図において、9は電子部品7の電源様子、101ま
電子部品7のグランド端子である。
In FIG. 2, reference numeral 9 indicates a power supply state of the electronic component 7, and 101 indicates a ground terminal of the electronic component 7.

第2図に示すような多層印刷配線板では、内層パターン
は電子部品7の共通電源や共通グランドの供給に使用す
ることが多い。ところが実装された電子部品7の電源や
グラン日こ接続されるべき端子の位置は、部品の種類や
回路接続によって、まちまちである。このような場合に
従来方式による多層印刷配線板製造方法では、内層パタ
ーンに接続されるべき電子部品端子の位置が変わる印刷
回路組立板ごとに、内層パターンのマスタフィルムを作
る必要があり内層用マスタフィルム製作費がかさむとと
もに、多層板積層工程は内層パターンが決定するまで行
うことができず、多層印刷配線板製作工期が長び〈主原
因であった。この発明はこれらの欠点を解消するために
なされたもので、電子部品の端子が挿入される内層パタ
ーンと非接触の第1のスルーホールと、内層パターンと
接続される第2のスルーホールと、この第1、第2のス
ルーホールを接続する表面層パターンとを設けることに
より内層パターンを標準化することができ、多層印刷配
線板の積層工程までをあらかじめ作業を終了させた半製
品として在庫しうる製造効率のよい多層印刷配線板のパ
ターン接続方法を提供するものである。
In a multilayer printed wiring board as shown in FIG. 2, the inner layer pattern is often used for supplying a common power source and a common ground to electronic components 7. However, the positions of the terminals to be connected to the power source and ground of the mounted electronic component 7 vary depending on the type of component and circuit connection. In such cases, in the conventional multilayer printed wiring board manufacturing method, it is necessary to create a master film for the inner layer pattern for each printed circuit assembly board in which the position of the electronic component terminal to be connected to the inner layer pattern changes. In addition to increasing film production costs, the multilayer board lamination process could not be carried out until the inner layer pattern was determined, which was the main reason for prolonging the production period for multilayer printed wiring boards. This invention was made to eliminate these drawbacks, and includes a first through hole that is not in contact with the inner layer pattern into which a terminal of an electronic component is inserted, a second through hole that is connected to the inner layer pattern, By providing a surface layer pattern that connects the first and second through holes, the inner layer pattern can be standardized, and the process up to the lamination process of the multilayer printed wiring board can be stocked as a semi-finished product. The present invention provides a pattern connection method for multilayer printed wiring boards with high manufacturing efficiency.

以下第3図〜第8図を用いてこの発明の一実施例につい
て説明する。
An embodiment of the present invention will be described below with reference to FIGS. 3 to 8.

第3図はこの発明の一実施例を説明するための多層印刷
配線板を使用した印刷回路組立板で、第4図は第3図の
斜視断面図である。第3図および第4図において、第2
図と同一または相当部分には同一符号を符してある。
FIG. 3 is a printed circuit assembly board using a multilayer printed wiring board for explaining one embodiment of the present invention, and FIG. 4 is a perspective sectional view of FIG. 3. In Figures 3 and 4, the second
The same or corresponding parts as in the figures are designated by the same reference numerals.

11は4層の多層印刷配線板で、2/4層内層パターン
には電子部品の共通電源が、3/4層内層パターンには
電子部品の共通グランドが供給されているものとする。
Reference numeral 11 denotes a four-layer multilayer printed wiring board, in which a common power source for electronic components is supplied to the 2/4 inner layer pattern, and a common ground for the electronic components is supplied to the 3/4 layer inner layer pattern.

12はIC,の電源端子、13はIC,のグランド端子
、14はIC2の電源様子、15はIC2のグランド端
子、16は2/4層内層パターン3に接続されたスルホ
ールメッキ穴、17は3/4層内層パターン4に接続さ
れたスルホールメツキ穴、18〜21は、それぞれ、ス
ルホールメツキ穴\1 6とIC端子12、スルホール
メッキ穴17とIC端子13、スルホールメッキ穴16
とIC端子14およびスルホールメッキ穴17とに端子
15を接続する外層パターンである。第5図を用いて多
層印刷配線板11をさらに説明する。
12 is the power supply terminal of the IC, 13 is the ground terminal of the IC, 14 is the power supply state of the IC2, 15 is the ground terminal of the IC2, 16 is the through hole plated hole connected to the 2/4 layer inner layer pattern 3, 17 is the 3 /4 layer The through-hole plating holes 18 to 21 connected to the inner layer pattern 4 are the through-hole plating hole \16 and the IC terminal 12, the through-hole plating hole 17 and the IC terminal 13, and the through-hole plating hole 16, respectively.
This is an outer layer pattern that connects the terminal 15 to the IC terminal 14 and the through-hole plating hole 17. The multilayer printed wiring board 11 will be further explained using FIG. 5.

第5図において、22は実際の製品には存在しない説明
用の格子状線である。格子状線22は一定の間隔で印刷
配線板1 1を区切っており印刷配線板11上のパター
ンやスルホールメッキ穴の位置を指示するもので、印刷
配線板11上のスルホールメッキ穴はすべてこの格子の
交点上に設けるものとする。23は内層パターンに接続
されない1′4茸および4/幻富の両外層パターンを接
続するスルホールメッキ穴である。
In FIG. 5, reference numeral 22 indicates grid lines for explanation that do not exist in the actual product. The grid lines 22 divide the printed wiring board 11 at regular intervals and indicate the pattern on the printed wiring board 11 and the positions of the through-hole plating holes. shall be placed on the intersection of Reference numeral 23 denotes a through-hole plating hole that connects both the outer layer patterns of 1'4 Mushroom and 4/Genfu which are not connected to the inner layer pattern.

2′4内層パターン3および3/4内層パターン4に接
続されたスルホールメッキ穴16および17は第3図に
示すようにあらかじめ定められた印刷配線板上の電子部
品7の配置に応じて、各電子部品のまわりの適当な位置
に設ける。
The through-hole plating holes 16 and 17 connected to the 2'4 inner layer pattern 3 and the 3/4 inner layer pattern 4 are formed respectively according to the predetermined arrangement of the electronic components 7 on the printed wiring board as shown in FIG. Install it at an appropriate position around the electronic components.

2′幻富内層パターン3および3/4層内層パターン4
はそれぞれ、スルホールメッキ穴16および17に対応
する位置を除き、任意の格子の交点にスルホ−ルメッキ
穴を設けた場合にも、そのスルホールが内層パターン3
および4に接続されないようにパターンは逃げてある。
2' Gentomi inner layer pattern 3 and 3/4 layer inner layer pattern 4
, except for the positions corresponding to the through-hole plating holes 16 and 17, even if through-hole plating holes are provided at the intersections of arbitrary grids, the through-holes will not be located in the inner layer pattern 3.
The pattern is omitted so that it is not connected to and 4.

第6図〜第8図にそれぞれのスルホールメッキ穴16,
17,23の断面図を示している。多層印刷配線板11
の内層パターン3および4から電子部品7への電気接続
は第4図を用いて説明すると、2ノ4層内層パターン3
〔または3/4層内層パターン4〕→内層パターンに接
続されているスルホールメッキ穴16〔または17〕→
外層パターン18〔または19〕→電子部品端子挿入用
スルホールメッキ穴6→電子部品端子12〔または13
〕という経路で接続する。
Through-hole plating holes 16,
17 and 23 are shown. Multilayer printed wiring board 11
The electrical connection from the inner layer patterns 3 and 4 to the electronic component 7 will be explained using FIG. 4.
[or 3/4 layer inner layer pattern 4] → Through-hole plating hole 16 [or 17] connected to the inner layer pattern →
Outer layer pattern 18 [or 19] → Through-hole plating hole 6 for inserting electronic component terminal → Electronic component terminal 12 [or 13]
].

以上述べたような構造にすれば印刷配線坂上に実装され
る電子部品の内層パターンへ接続する端子位置が変化し
ても、それぞれの内層パターンへ接続するスルホールメ
ッキ穴および内層パターンへ接続しないスルホールメッ
キ穴の位置が決まっているので、2/4または3′4層
内層パターンのパターンエッチング用マスタフィルムは
パターン形状が定まる。
With the structure described above, even if the position of the terminal connected to the inner layer pattern of the electronic component mounted on the printed wiring slope changes, there will be no through-hole plating holes that connect to each inner layer pattern and through-hole plating that does not connect to the inner layer pattern. Since the positions of the holes are determined, the pattern shape of the master film for pattern etching of the 2/4 or 3'4 inner layer pattern is determined.

したがって内層パターン用マスタフィルムは印刷配線板
11の外形状に応じた2/4または3′4層用をそれぞ
れ1種類製作するだけでよい。さらには、それぞれの内
層パターンが定まっていることから、1/4および4/
4層は、エッチングをしない銅張りのまま、2/4およ
び3/4層はそれぞれエッチング加工を施したもの、を
競層した状態で所定の多層印刷配線板の素材として取扱
うことができる。そして、印刷配線板上の実装部品が決
定し、−電気回路接続が決定した段階から、通常の両面
銅張印刷配線板と全く同様の製造工程を経ることによっ
て多層印刷配線板を製造することができる。もちろん、
1/4層外層パターン18や19等の外層パターンは他
の電気回路接続用外層パタ−ン2と同じエッチング工程
で同時に形成されることはいうまでもない。以上のよう
にこの発明の一実施例によれば従来のように、実装部品
の内層パターンへの綾続端子位置が変わるごとに内層パ
ターン用マスタフィルムを作る必要はなくマスタフィル
ム作成費用が低減できる。
Therefore, it is only necessary to produce one type of master film for inner layer patterns for 2/4 or 3'4 layers depending on the outer shape of the printed wiring board 11. Furthermore, since each inner layer pattern is fixed, 1/4 and 4/4
The four layers are copper-plated without etching, and the 2/4 and 3/4 layers are each etched, so that they can be used as materials for a predetermined multilayer printed wiring board. Then, from the stage where the components to be mounted on the printed wiring board have been determined and the electrical circuit connections have been determined, a multilayer printed wiring board can be manufactured by going through the manufacturing process that is exactly the same as that of a normal double-sided copper-clad printed wiring board. can. of course,
It goes without saying that the outer layer patterns such as the 1/4 layer outer layer patterns 18 and 19 are formed at the same time as the other electric circuit connection outer layer patterns 2 in the same etching process. As described above, according to an embodiment of the present invention, there is no need to create a master film for the inner layer pattern every time the position of the twill connection terminal to the inner layer pattern of the mounted component changes, as is the case in the past, and the cost of creating the master film can be reduced. .

多層板としての積層工程まではあらかじめ作業を進めて
素材的に取扱うことができる。すなわち、多層印刷配線
板の半製品化が可能であり、その量産効果と工場負荷の
平滑化および工期短縮等による原低効果が期待できる。
なお以上は標準的な4層多層印刷配線板について説明し
たが、この発明はこれに限らず、内層パターンが共通的
なものであれば4層に限らずいかなる層数の多層印刷配
線板にも適用できる。
It is possible to proceed with the work up to the lamination process as a multi-layer board in advance and handle it in terms of materials. That is, it is possible to semi-finish a multilayer printed wiring board, and it is expected to have a mass production effect and a cost reduction effect due to smoothing of the factory load and shortening of the construction period.
Although the above description has been about a standard four-layer multilayer printed wiring board, this invention is not limited to this, and can be applied to multilayer printed wiring boards with any number of layers, not just four layers, as long as the inner layer pattern is common. Applicable.

また、第5図に格子状線22で示す格子のすべての交点
上に表裏導通用のスルホールメッキ穴23をあらかじめ
設ける印刷配線板製造方式を行えば多層印刷配線板の積
層工程のみならず、スルホール穴明けおよびスルホール
メツキ工程、さらに場合によっては印刷配線板の端子部
メッキ工程等の処理をした状態まで半製品化することも
可能である。以上のようにこの発明によれば内層パター
ンと電子部品端子の接続を直接、電子部品端子挿入穴で
行なわず、部品端子挿入穴以外の固定位鷹のスルホール
メッキ穴を介して接続するようにしたので、内層パター
ンを標準化でき、内層パターン設計および内層パターン
用マスタフイルム製作費の低減と多層板の積層工程をあ
らかじめ処理し素材的に扱うことによって量産効果、工
場負荷の平滑化および工期短縮による原低効果がある。
In addition, if a printed wiring board manufacturing method is used in which through-hole plating holes 23 for front and back conduction are provided in advance on all the intersection points of the grid shown by grid lines 22 in FIG. It is also possible to produce a semi-finished product through the processes of drilling and through-hole plating, and in some cases, plating the terminals of printed wiring boards. As described above, according to the present invention, the inner layer pattern and the electronic component terminal are not connected directly through the electronic component terminal insertion hole, but are connected through the through-hole plating hole of the fixed position other than the component terminal insertion hole. Therefore, the inner layer pattern can be standardized, reducing the cost of inner layer pattern design and master film production for the inner layer pattern, and by processing the lamination process of multilayer boards in advance and handling them as materials, it is possible to increase the efficiency of mass production, smooth the factory load, and shorten the construction period. It has low effectiveness.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の多層印刷配線板を使用した印刷回路組立
板の電子部品端子挿入用スルホールメッキ穴部の断面図
、第2図は多層印刷配線板を使用した印刷回路組立板の
一例を示す説明図、第3図はこの発明の一実施例を設明
するための多層印刷配線板を使用した印刷回路組立板を
示す説明図、第4図は第3図の電子部品端子挿入穴付近
の断面拡大図、第5図は第3図の多層印刷配線板を説明
するための図、第6図〜第8図は第3図に示す印刷配線
板中の内層援競用スルホールメッキ穴の断面拡大図であ
る。 図において、2〜5はそれぞれ1/4層〜4/4層パタ
ーン、6は電子部品端子挿入用スルホールメッキ穴、7
は電子部品、11は4層多層印刷配線板、16および1
7は内層接続用スルホールメツキ穴、18〜21は1/
4層外層パターン、23は内層パターンにも接続されな
いスルホールメッキ穴である。 なお、同一部分および相当部分には同一符号を付して示
してある。第1図 第6図 第2図 第3図 第7図 第8図 第4図 第5図
Figure 1 is a cross-sectional view of a through-hole plating hole for inserting an electronic component terminal in a printed circuit assembly board using a conventional multilayer printed wiring board, and Figure 2 shows an example of a printed circuit assembly board using a multilayer printed wiring board. FIG. 3 is an explanatory diagram showing a printed circuit assembly board using a multilayer printed wiring board for establishing an embodiment of the present invention, and FIG. An enlarged cross-sectional view, FIG. 5 is a diagram for explaining the multilayer printed wiring board shown in FIG. 3, and FIGS. 6 to 8 are cross sections of through-hole plating holes for inner layer reinforcement in the printed wiring board shown in FIG. 3. It is an enlarged view. In the figure, 2 to 5 are 1/4 layer to 4/4 layer patterns, 6 is a through-hole plating hole for inserting an electronic component terminal, and 7 is a through-hole plated hole for inserting an electronic component terminal.
1 is an electronic component, 11 is a 4-layer multilayer printed wiring board, 16 and 1
7 is a through-hole plating hole for inner layer connection, 18 to 21 are 1/
In the four-layer outer layer pattern, 23 is a through-hole plating hole that is not connected to the inner layer pattern either. Note that the same parts and corresponding parts are indicated by the same reference numerals. Figure 1 Figure 6 Figure 2 Figure 3 Figure 7 Figure 8 Figure 4 Figure 5

Claims (1)

【特許請求の範囲】[Claims] 1 多層印刷配線板の内層パターンと該配線板に実装さ
れる電子部品とを電気的に接続するためのパターン接続
構造において、上記多層印刷配線板に内層パターンと非
接触に形成され、上記電子部品の端子が挿入される第1
のスルーホールと、上記多層印刷配線板の電子部品の配
置に応じて決められた所定位置に設けられた上記内層パ
ターンと接続された第2のスルーホールと、上記多層印
刷配線板の表面に設けられ上記両スルーホールを電気的
に接続する表面層パターンとを備えたことを特徴とする
多層印刷配線板のパターン接続構造。
1 In a pattern connection structure for electrically connecting an inner layer pattern of a multilayer printed wiring board and an electronic component mounted on the wiring board, the pattern connection structure is formed on the multilayer printed wiring board without contacting the inner layer pattern, and the electronic component is formed on the multilayer printed wiring board without contacting the inner layer pattern. The first terminal into which the terminal of
a second through hole connected to the inner layer pattern provided at a predetermined position determined according to the arrangement of electronic components of the multilayer printed wiring board, and a second through hole provided on the surface of the multilayer printed wiring board. and a surface layer pattern electrically connecting both of the through holes.
JP52018922A 1977-02-22 1977-02-22 Pattern connection structure of multilayer printed wiring board Expired JPS6038878B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP52018922A JPS6038878B2 (en) 1977-02-22 1977-02-22 Pattern connection structure of multilayer printed wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP52018922A JPS6038878B2 (en) 1977-02-22 1977-02-22 Pattern connection structure of multilayer printed wiring board

Publications (2)

Publication Number Publication Date
JPS53109173A JPS53109173A (en) 1978-09-22
JPS6038878B2 true JPS6038878B2 (en) 1985-09-03

Family

ID=11985100

Family Applications (1)

Application Number Title Priority Date Filing Date
JP52018922A Expired JPS6038878B2 (en) 1977-02-22 1977-02-22 Pattern connection structure of multilayer printed wiring board

Country Status (1)

Country Link
JP (1) JPS6038878B2 (en)

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JP6192515B2 (en) * 2013-05-16 2017-09-06 株式会社ソフイア Game machine
JP6232572B2 (en) * 2013-05-16 2017-11-22 株式会社ソフイア Game machine
JP6192513B2 (en) * 2013-05-16 2017-09-06 株式会社ソフイア Game machine

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50144077A (en) * 1974-05-10 1975-11-19

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5421734Y2 (en) * 1973-08-27 1979-08-01

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50144077A (en) * 1974-05-10 1975-11-19

Also Published As

Publication number Publication date
JPS53109173A (en) 1978-09-22

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