JPH03178193A - Multilayer printed board - Google Patents
Multilayer printed boardInfo
- Publication number
- JPH03178193A JPH03178193A JP1316569A JP31656989A JPH03178193A JP H03178193 A JPH03178193 A JP H03178193A JP 1316569 A JP1316569 A JP 1316569A JP 31656989 A JP31656989 A JP 31656989A JP H03178193 A JPH03178193 A JP H03178193A
- Authority
- JP
- Japan
- Prior art keywords
- power supply
- printed circuit
- circuit board
- conductive film
- pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005670 electromagnetic radiation Effects 0.000 claims description 8
- 239000000758 substrate Substances 0.000 claims description 3
- 239000003990 capacitor Substances 0.000 abstract description 13
- 239000000463 material Substances 0.000 abstract description 7
- 238000003672 processing method Methods 0.000 abstract description 7
- 238000010586 diagram Methods 0.000 description 10
- 230000000694 effects Effects 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 230000002411 adverse Effects 0.000 description 2
- 239000011889 copper foil Substances 0.000 description 2
- 238000005553 drilling Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 230000002265 prevention Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 239000007787 solid Substances 0.000 description 2
- 240000001973 Ficus microcarpa Species 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000011888 foil Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はプリント基板や多層プリント基板に係り、特に
、高密度実装を行なっても回路素子の動作を安定ならし
めるに好適なプリント基板や多層プリント基板基板に関
する。[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to printed circuit boards and multilayer printed circuit boards, and in particular, to printed circuit boards and multilayer circuit boards suitable for stabilizing the operation of circuit elements even when high-density mounting is performed. It relates to a printed circuit board.
一枚のプリント基板に搭載される電子部品の数が増大し
、プリント基板も多層化されてきている。The number of electronic components mounted on a single printed circuit board is increasing, and printed circuit boards are also becoming multilayered.
この多層プリント基板は、−面全面に銅箔がメツキされ
た絶縁層のｆＩ箔に必要な配線パターン等をエツチング
したちの複数を、互いに位置合わせして圧接し、必要ケ
所に導通穴を開け、この導通穴の内壁に導通メツキを施
して各層における配線パターンを接続し配線を立体構造
としている。この導通穴をスルーホールという。This multilayer printed circuit board is made by etching the necessary wiring patterns etc. on the insulating layer fI foil, which is plated with copper foil on the entire negative side, aligning and pressing together, and drilling holes where necessary. Conductive plating is applied to the inner wall of this conductive hole to connect the wiring patterns in each layer to form a three-dimensional wiring structure. This conductive hole is called a through hole.
第５図は、多層プリント基板の模式図である。FIG. 5 is a schematic diagram of a multilayer printed circuit board.
この第５図の例では、６層のプリント基板を例示してい
るが、絶縁層１０．５０の表面と絶縁層１０．２０゜３
０．４０．５０．６０間の導電パターンの内、中心２Ｎ
の広い面積のいわゆるベタパターン２１．２２が電源層
であり、電源１ｉ２１が例えばプラス５Ｖに接続され、
電源層２２がこれと異なる電位例えばアース電位に接続
される。他の導電パターン１１．１２，３１．３２は信
号配線パターンであり、他層間の信号配線パターンや電
源層と接続される場合はスルーホール１を介して行なわ
れる。In the example shown in FIG. 5, a six-layer printed circuit board is illustrated, and the surface of the insulating layer 10.50 and the surface of the insulating layer 10.20°3
Among the conductive patterns between 0.40.50.60, center 2N
The so-called solid patterns 21 and 22 with a large area are the power supply layer, and the power supply 1i21 is connected to, for example, +5V,
The power supply layer 22 is connected to a different potential, such as ground potential. The other conductive patterns 11.12, 31.32 are signal wiring patterns, and are connected to the signal wiring patterns between other layers or the power supply layer through the through holes 1.
第６図は、スルーホール部における信号配線パターン、
電源層パターンとの接続状態の様子を例示する図である
。このスルーホールは、多層プリント基板作製後に所定
位置に穴を開け、この穴の内部に導電メツキを施すこと
で、作製される。そして、このスルーホール１に、第７
図に示す様に、例えばＩＣ１０１の足１０２を挿入し半
田付けすることで、電子部品を接続する。尚、プリント
基板上の電子部品は、電源層２１．２２に接続されたス
ルーホールから給電されるが、電源が外部にある場合に
は、スルーホールにコネクタを取り付け、このコネクタ
からも受電することができる。Figure 6 shows the signal wiring pattern in the through-hole section,
FIG. 3 is a diagram illustrating a state of connection with a power layer pattern. This through hole is produced by drilling a hole at a predetermined position after producing the multilayer printed circuit board, and applying conductive plating to the inside of the hole. Then, in this through hole 1, the seventh
As shown in the figure, the electronic components are connected by, for example, inserting and soldering the legs 102 of the IC 101. Note that the electronic components on the printed circuit board are supplied with power from the through holes connected to the power supply layers 21 and 22, but if the power source is external, a connector can be attached to the through hole and power can also be received from this connector. I can do it.
従来のプリント基板は、信号配線パターンをエツチング
する導電膜においては、信号配線パターン以外は余白部
としてその部分の導電膜は剥離し、絶縁層が露出しこれ
が他層と圧接される様になっている。In conventional printed circuit boards, in the conductive film where the signal wiring pattern is etched, the area other than the signal wiring pattern is left as a margin, and the conductive film in that area is peeled off, exposing the insulating layer and coming into pressure contact with other layers. There is.
この種の技術として関連するものには、特公昭６３−２
３６７７号、特公昭６３−５８３９４号が挙げられる。Related technologies of this type include:
No. 3677 and Japanese Patent Publication No. 63-58394.
第８図は、電子部品１０１に電源１０３から給電する場
合の等価回路である。電子部品の動作速度が早くなると
、電源回路のインダクタンス分１０４が大きくなり、電
子部品の受電電圧が降下する。特に、複数の電子部品が
共通の電源に接続される場合は、この電圧降下の影響を
互いに及ぼし合うことになり、全体の回路動作が不安定
になる。そこで、電子部品近傍では、インダクタンス分
が小さく、また、キャパシタンス分１０５を持つような
構成にするのが好ましい。ディスクリートのキャパシタ
は、構造上リアクタンス分を持つので、上記の特性を得
られない。このため、デイクスリートのキャパシタでは
なく、第５図に示したように、広い面積のベタパターン
で形成され絶縁層を介して対面する電源層２１．２２を
キャパシタとして使用するのが好ましい。これは、この
キャパシタ１０５がインダクタンス分を持たないことに
よる。FIG. 8 is an equivalent circuit when power is supplied to the electronic component 101 from the power supply 103. As the operating speed of the electronic component increases, the inductance 104 of the power supply circuit increases, and the voltage received by the electronic component decreases. In particular, when a plurality of electronic components are connected to a common power source, the voltage drop affects each other, making the overall circuit operation unstable. Therefore, it is preferable to have a structure in which the inductance is small and the capacitance is 105 near the electronic component. Discrete capacitors have a reactance component due to their structure, so the above characteristics cannot be obtained. Therefore, as shown in FIG. 5, it is preferable to use power supply layers 21 and 22, which are formed in a solid pattern over a wide area and face each other through an insulating layer, as a capacitor instead of using a discrete capacitor. This is because this capacitor 105 has no inductance.
近年は高集積化された半導体素子が多用され、１枚のプ
リント基板に搭載される電子部品の数も膨大になり、従
来に比べて高密度実装がされる様になってきている。つ
まり、従来よりも更にキャパシタンス値を大きくしない
と、個々の電子部品相互で悪影響を及ぼし合うことにな
る。特に、半導体集積素子間での影響が大きい。そこで
、キャパシタンスを大きくするために、プリント基板を
構成する絶縁物として誘電率が大きく、厚み寸法の小さ
いものを使用する必要が生じるが、これらの対策は、材
質や加工法により限界があり、また、コストアップの要
因になる。In recent years, highly integrated semiconductor elements have been widely used, and the number of electronic components mounted on a single printed circuit board has also increased, leading to higher density mounting than ever before. In other words, unless the capacitance value is increased further than before, the individual electronic components will have an adverse effect on each other. In particular, the influence between semiconductor integrated devices is large. Therefore, in order to increase the capacitance, it is necessary to use an insulator that has a high dielectric constant and a small thickness for the printed circuit board, but these measures have limitations depending on the material and processing method. , which causes an increase in costs.
本発明の目的は、従来と同一の材質や加工法を使用しし
かも低コストで大きなキャパシタンスを得ることのでき
るプリント基板を提供することにある。An object of the present invention is to provide a printed circuit board that uses the same materials and processing methods as conventional ones and can provide a large capacitance at low cost.
上記目的は、導電膜を一面側に有する絶縁層を少なくと
も４層積層し、内側２層の導電膜を電源層にすると共に
他の層の導電膜に信号線パターンを作成した多層プリン
ト基板において、信号線パターンを作成する層の信号線
以外の余白部の導電膜を削除せずに残し、この導電膜余
白部を隣接する電源層と異なる電位の電源層に接続し電
源膜パターンとして使用することで、達成される。The above object is to provide a multilayer printed circuit board in which at least four insulating layers each having a conductive film on one side are laminated, the inner two conductive films are used as power supply layers, and signal line patterns are formed on the other conductive films. The conductive film in the margins other than the signal lines of the layer where the signal line pattern is created is left without being deleted, and the conductive film margins are connected to a power supply layer with a different potential from the adjacent power supply layer and used as a power supply film pattern. And it will be achieved.
また、上記目的は、対面する電源膜の間に形成されるキ
ャパシタンスを利用すべく作製されるプリント基板であ
って、信号配線パターン以外の領域に前記キャパシタン
スとして利用される対面する導電膜パターンを作製し該
導電膜パターンを全キャパシタンス値が最大となるよう
に結線することで、達成される。Further, the above object is to provide a printed circuit board manufactured to utilize the capacitance formed between facing power supply films, in which a facing conductive film pattern used as the capacitance is manufactured in an area other than the signal wiring pattern. This is achieved by connecting the conductive film patterns so that the total capacitance value is maximized.
更にまた、上記目的は、プリント基板の表面に絶縁膜を
介して電磁放射防止用導電膜を積層したプリント基板に
おいて、前記電磁放射防止用導電膜を該プリント基板の
電源層に接続し電位の異なる電源層間のキャパシタンス
値を増大させることで、達成される。Furthermore, the above object is to provide a printed circuit board in which a conductive film for preventing electromagnetic radiation is laminated on the surface of the printed circuit board via an insulating film, in which the conductive film for preventing electromagnetic radiation is connected to a power supply layer of the printed circuit board, and the electrical potential is different from that of the printed circuit board. This is achieved by increasing the capacitance value between the power layers.
従来は、専用の電源層として用いられた対面する導電膜
のみをキャパシタンスとして利用していたが、本発明で
は、従来は信号配線パターンの余白部として導電膜を剥
離していた領域の導電膜を残しこれを電源層と接続し実
質的にキャパシタの面積を広げ、あるいは電磁放射防止
膜を電源層と接続し実質的にキャパシタの面積を広げる
ことで、大きなキャパシタンスを得ている。このため、
絶縁層の材質やその加工法も同一であり、コストを高め
ることなく目的を達成することができる。Conventionally, only the facing conductive film used as a dedicated power supply layer was used as capacitance, but in the present invention, the conductive film in the area where the conductive film was conventionally peeled off as a margin of the signal wiring pattern is removed. A large capacitance can be obtained by connecting this layer to the power layer, essentially expanding the area of the capacitor, or by connecting the electromagnetic radiation prevention film to the power layer, essentially expanding the area of the capacitor. For this reason,
The material of the insulating layer and its processing method are also the same, and the purpose can be achieved without increasing cost.
以下、本発明の好適な実施例を第１図乃至第４図を参照
して説明する。Hereinafter, preferred embodiments of the present invention will be described with reference to FIGS. 1 to 4.
第■図は、本発明の一実施例に係る多層（本実施例では
６層）プリント基板の模式断面図である。FIG. 3 is a schematic cross-sectional view of a multilayer (six layers in this embodiment) printed circuit board according to an embodiment of the present invention.
プリント基板の面積は、搭載実装される電子部品やこれ
らを接続する信号配線パターンの占める面積により決め
られるが、面付実装部品が多用される近年の多層プリン
ト基板にあっては、回路チエツクの為に必ず外層に置く
べきパターンがあり、内層の信号配線パターンは、通常
、密度が低くなり、余白部分（信号配線パターンでない
領域）の面積の占める割合は、６０〜８０パーセントに
も達するのが普通である。The area of a printed circuit board is determined by the area occupied by the electronic components to be mounted and the signal wiring patterns that connect them, but in recent years multilayer printed circuit boards that often use surface-mounted components, it is necessary to check the circuit board. There is a pattern that must be placed on the outer layer, and the density of the signal wiring pattern on the inner layer is usually lower, and the area occupied by the blank area (area that is not a signal wiring pattern) usually reaches 60 to 80%. It is.
そこで、本実施例では、第１図に示す様に、表面から２
層目の信号配線パターン１２．３１を設けた導電膜の余
白部分の導電膜１２１，３１１を削除せずに残し、導電
膜パターン１２１をスルーホール１′を介して電源層２
２に接続し、導電膜パターン３１１をスルーホールｌを
介して電源層２１に接続する。第２図は、導電膜パター
ン１２１．３１１と電源層２１．２２との関係を示す図
である。本実施例によれば、導電膜パターン１２１ と
電源層２１との間にキャパシタＣ１が形成され、導電膜
パターン３１１と電源膜２２との間にキャパシタＣ３が
形成され、これらのキャパシタＣＩ、Ｃ３が、電源層２
１．２２間のキャパシタＣ２に並列に接続された形にな
る。第３図は、このキャパシタＣ１，Ｃ２，Ｃ３の等価
回路図である。つまり、本実施例における等価キャパシ
タンスＣは、
Ｃ＝Ｃ１＋Ｃ２＋Ｃ３
となる。第１図において、絶縁基板２０．４０はプリプ
レグと呼ばれ、銅箔を持つ基板１０，３０．５０と比べ
その厚さは約１／２である。そこで、この条件と、導電
膜パターン１２１，３１１が電源層２１．２２の６０〜
８０パーセントの面積であることと、材質及び加工法が
従来と同じであることを勘案して上記キャパシタンスＣ
を求めると、
Ｃｌ＝Ｃ３
二Ｃ２Ｘ（０，６〜ｏ、８）ｘｉ／ （１／２）＝Ｃ２
Ｘ（１，２〜１．６）
となるので、
Ｃ＝Ｃ１＋Ｃ２＋Ｃ３
＝−Ｃ２Ｘ （１，２〜１．６）Ｘ２＋Ｃ２＝Ｃ２Ｘ（
３，４〜４．２）
となる。つまり、本実施例によれば、従来はキャパシタ
ンスがＣ２だけであったのに対し、その３．４〜４．２
倍のキャパシタンス値を得ることができる。Therefore, in this embodiment, as shown in FIG.
The conductive film 121, 311 in the margin of the conductive film provided with the signal wiring pattern 12.31 of the layer is left without being removed, and the conductive film pattern 121 is inserted into the power supply layer 2 through the through hole 1'.
2, and the conductive film pattern 311 is connected to the power supply layer 21 via the through hole l. FIG. 2 is a diagram showing the relationship between the conductive film pattern 121.311 and the power supply layer 21.22. According to this embodiment, a capacitor C1 is formed between the conductive film pattern 121 and the power supply layer 21, a capacitor C3 is formed between the conductive film pattern 311 and the power supply film 22, and these capacitors CI and C3 are , power layer 2
It is connected in parallel to the capacitor C2 between 1.22 and 22. FIG. 3 is an equivalent circuit diagram of the capacitors C1, C2, and C3. That is, the equivalent capacitance C in this example is as follows: C=C1+C2+C3. In FIG. 1, an insulating substrate 20.40 is called a prepreg, and its thickness is approximately 1/2 that of the copper foil substrate 10, 30.50. Therefore, under these conditions and the conductive film patterns 121, 311 are
Considering that the area is 80% and the material and processing method are the same as before, the above capacitance C
When calculating, Cl=C3 2C2X(0,6~o,8)xi/ (1/2)=C2
X (1,2~1.6), so C=C1+C2+C3 =-C2X (1,2~1.6)X2+C2=C2X(
3,4-4.2). In other words, according to this embodiment, whereas conventionally the capacitance was only C2, the capacitance is 3.4 to 4.2.
It is possible to obtain twice the capacitance value.
次に、本発明の第２実施例について述べるが、この実施
例は図示するまでもないので、言葉でのみ説明する。高
速動作を行なう電子部品が搭載されたプリント基板の信
号配線からは、電子部品動作時に数百メガヘルツ帯に及
ぶ電磁放射がされ、これが他の電子部品に悪影響を及ぼ
す。従って、この電磁放射を防止するために、プリント
基板の表面層と裏面層の全面を、夫々絶縁層を介して銅
ペースト等の導電膜で覆う（スルーホールは除く）。こ
の場合、電磁放射防止用の導電膜を電源層と接続するこ
とで、プリント基板の等価キャパシタを大きくすること
ができる。Next, a second embodiment of the present invention will be described, but since this embodiment does not need to be illustrated, it will be described only in words. Signal wiring on a printed circuit board on which electronic components that operate at high speed are mounted emit electromagnetic radiation in the hundreds of megahertz band when the electronic components operate, which adversely affects other electronic components. Therefore, in order to prevent this electromagnetic radiation, the entire surfaces of the front and back layers of the printed circuit board are covered with a conductive film such as copper paste via an insulating layer (excluding through holes). In this case, the equivalent capacitor of the printed circuit board can be increased by connecting the conductive film for electromagnetic radiation prevention to the power supply layer.
第４図は、本発明の別の実施例に係るプリント基板の断
面図である。本実施例は１層のプリント基板であり、こ
の両面に異なる電位の電源層を設けるに当たり、なるべ
く広い面積で両電源層が重なり合うようにしている。こ
れにより、大きな等価キャパシタンスを得ることが可能
となる。FIG. 4 is a sectional view of a printed circuit board according to another embodiment of the present invention. This embodiment is a one-layer printed circuit board, and when providing power supply layers with different potentials on both sides, the two power supply layers are made to overlap over as wide an area as possible. This makes it possible to obtain a large equivalent capacitance.
本発明によれば、コストを増大させることなく、従来と
同一材料、同一加工法によって大きな等価キャパシタン
スを有するプリント基板を得ることができるという効果
がある。According to the present invention, there is an effect that a printed circuit board having a large equivalent capacitance can be obtained using the same materials and the same processing method as conventional ones without increasing costs.
第１図は本発明の一実施例に係る多層プリント基板の模
式断面図、第２図は第１図の導電膜パターンと電源層の
関係を示す図、第３図は第１図に示す電源回路の等価回
路図、第４図は本発明の別実施例に係るプリント基板の
断面図、第５図は従来の多層プリント基板の模式断面図
、第６図は第５図に示すスルーホールの説明図、第７図
はプリント基板に電子部品を搭載する所を示す図、第８
図は従来の多層プリント基板の電源回路の等価回路図で
ある。
■、１′・・・スルーホール、１０，２０，３０，４０
．５０・・・絶縁層、１１，１２，３１．３２・・・信
号配線パターン、２１ 、２２・・・電源層、１２１，
３１１・・・導電膜パターン。FIG. 1 is a schematic cross-sectional view of a multilayer printed circuit board according to an embodiment of the present invention, FIG. 2 is a diagram showing the relationship between the conductive film pattern in FIG. 1 and the power supply layer, and FIG. 3 is the power supply shown in FIG. An equivalent circuit diagram of the circuit, FIG. 4 is a sectional view of a printed circuit board according to another embodiment of the present invention, FIG. 5 is a schematic sectional view of a conventional multilayer printed circuit board, and FIG. 6 is a diagram of the through hole shown in FIG. Explanatory diagram, Figure 7 is a diagram showing where electronic components are mounted on the printed circuit board, Figure 8
The figure is an equivalent circuit diagram of a power supply circuit of a conventional multilayer printed circuit board. ■, 1'...Through hole, 10, 20, 30, 40
．． 50... Insulating layer, 11, 12, 31. 32... Signal wiring pattern, 21, 22... Power supply layer, 121,
311... Conductive film pattern.
Claims (7)
層し、内側２層の導電膜を電源層にすると共に他の層の
導電膜に信号線パターンを作成した多層プリント基板に
おいて、信号線パターンを作成する層の信号線以外の余
白部の導電膜を削除せずに残し、この導電膜余白部を隣
接する電源層と異なる電位の電源層に接続し電源膜パタ
ーンとして使用するようにしたことを特徴とする多層プ
リント基板。1. In a multilayer printed circuit board in which at least four insulating layers each having a conductive film on one side are laminated, the inner two conductive films are used as power supply layers, and signal line patterns are created on the other conductive films, the signal line pattern is formed. The conductive film in the blank area other than the signal lines of the layer to be created is left without being deleted, and this conductive film blank area is connected to a power layer with a different potential from the adjacent power layer to be used as a power supply film pattern. Features a multilayer printed circuit board.
数積層し、内側２層の導電膜を電源層にすると共に他の
層の導電膜に信号線パターンを作成した多層プリント基
板において、信号線パターンを作成する層の信号線以外
の余白部の導電膜を削除せずに残し、この導電膜余白部
を隣接する電源層と異なる電位の電源層に接続し電源膜
パターンとして使用するようにしたことを特徴とする多
層プリント基板。2. In a multilayer printed circuit board, a plurality of insulating substrates having conductive films on both sides are laminated with insulating layers interposed between them, the inner two conductive films are used as power supply layers, and signal line patterns are created on the conductive films of other layers. The conductive film in the blank area other than the signal line of the layer to be patterned is left without being deleted, and this conductive film blank area is connected to a power layer with a different potential from the adjacent power layer to be used as a power supply film pattern. A multilayer printed circuit board characterized by:
導電膜パターンを電源膜パターンとして残すにあたり隣
接する層の電源膜パターンとの重複領域を広く設定する
と共に隣接する電源膜とは異なる電位の電源膜としたこ
とを特徴とする多層プリント基板。3. In a multilayer printed circuit board, when leaving a conductive film pattern other than a signal line pattern as a power supply film pattern, the overlapping area with the power supply film pattern of an adjacent layer is set wide, and the power supply film has a different potential from that of the adjacent power supply film. A multilayer printed circuit board featuring:
ーンとする請求項１乃至請求項３のいずれかに記載の多
層プリント基板において、集積回路素子を搭載する信号
配線パターンの周囲を前記電源膜パターンとしたことを
特徴とする多層プリント基板。4. 4. The multilayer printed circuit board according to claim 1, wherein the conductive film in an area other than the signal wiring pattern is a power supply film pattern, wherein the signal wiring pattern on which an integrated circuit element is mounted is surrounded by the power supply film pattern. A multilayer printed circuit board characterized by:
利用する作製されるプリント基板であって、信号配線パ
ターン以外の領域に前記キャパシタンスとして利用され
る対面する導電膜パターンを作製し該導電膜パターンを
全キャパシタンス値が最大となるように結線したことを
特徴とするプリント基板。5. A printed circuit board manufactured using capacitance formed between facing power supply films, in which a facing conductive film pattern used as the capacitance is created in an area other than the signal wiring pattern, and the conductive film pattern is completely covered with the conductive film pattern. A printed circuit board characterized in that the wires are connected to maximize the capacitance value.
電源膜パターンと信号配線パターンとを作成したプリン
ト基板において、電源膜間の重複領域を広くとったこと
を特徴とするプリント基板。6. 1. A printed circuit board having at least two conductive films facing each other and having a power supply film pattern and a signal wiring pattern formed on the conductive films, characterized in that the overlapping area between the power supply films is wide.
用導電膜を積層したプリント基板において、前記電磁放
射防止用導電膜を該プリント基板の電源層に接続し電位
の異なる電源層間のキャパシタンス値を増大させたこと
を特徴とするプリント基板。7. In a printed circuit board in which a conductive film for preventing electromagnetic radiation is laminated on the surface of the printed circuit board via an insulating film, the conductive film for preventing electromagnetic radiation is connected to a power layer of the printed circuit board to increase the capacitance value between power layers having different potentials. A printed circuit board characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1316569A JPH03178193A (en) | 1989-12-07 | 1989-12-07 | Multilayer printed board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1316569A JPH03178193A (en) | 1989-12-07 | 1989-12-07 | Multilayer printed board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03178193A true JPH03178193A (en) | 1991-08-02 |
Family
ID=18078558
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1316569A Pending JPH03178193A (en) | 1989-12-07 | 1989-12-07 | Multilayer printed board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03178193A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0715148A (en) * | 1993-06-11 | 1995-01-17 | Internatl Business Mach Corp <Ibm> | Multilayer circuit board |
| JP2002344149A (en) * | 2001-05-15 | 2002-11-29 | Oki Electric Ind Co Ltd | Wiring structure board |
| JP2010199352A (en) * | 2009-02-26 | 2010-09-09 | Sekisui Jushi Co Ltd | Circuit board equipped with radiation pattern and radiation pattern forming method |
-
1989
- 1989-12-07 JP JP1316569A patent/JPH03178193A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0715148A (en) * | 1993-06-11 | 1995-01-17 | Internatl Business Mach Corp <Ibm> | Multilayer circuit board |
| JP2513443B2 (en) * | 1993-06-11 | 1996-07-03 | インターナショナル・ビジネス・マシーンズ・コーポレイション | Multilayer circuit board assembly |
| JP2002344149A (en) * | 2001-05-15 | 2002-11-29 | Oki Electric Ind Co Ltd | Wiring structure board |
| JP4694035B2 (en) * | 2001-05-15 | 2011-06-01 | Ｏｋｉセミコンダクタ株式会社 | Wiring structure board |
| JP2010199352A (en) * | 2009-02-26 | 2010-09-09 | Sekisui Jushi Co Ltd | Circuit board equipped with radiation pattern and radiation pattern forming method |
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