JP4694035B2 - Wiring structure board - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a wiring structure board that can reduce EMI (Electro Magnetic Interference), and more particularly to a wiring structure board that can reduce unnecessary radiation from a printed circuit board on which electronic circuit components are mounted.
[0002]
[Prior art]
FIG. 7 shows a basic configuration example of a conventional printed wiring board mounted with a digital circuit. FIG. 7A is a perspective view partially showing a part of wiring of an electronic component constituting the digital circuit and a substrate on which the wiring is formed. FIG. 7B is a cross-sectional view taken along the direction in which current flows in the structure of FIG. According to FIG. 7, a multilayer substrate (also referred to as a multilayer board) having a stacked structure of a first insulating layer 102, a ground layer 104, an interlayer insulating layer 106, a power supply layer 108 and a second insulating layer 110 in order from the upper surface side. A first signal wiring pattern 112 formed on the first insulating layer 102, a second signal wiring pattern 114 formed on the back side of the second insulating layer 110, and a hole penetrating the multilayer substrate, The signal wall 116 is embedded in a conductive material or covered by plating or the like. The first signal wiring pattern 112 and the second signal wiring pattern 114 are electrically connected by the signal via 116. The first signal wiring pattern 112 and the second signal wiring pattern 114 have a microstrip line structure, and are used, for example, as wiring for connecting electronic components.
[0003]
[Problems to be solved by the invention]
However, in the wiring structure substrate having the above-described structure, unnecessary electromagnetic waves are radiated. Referring to the configuration example of FIG. 7, in this structure, the first and second signal wiring patterns 112 and 114 are both formed on the surface of a wiring structure substrate (also simply referred to as a substrate). The periphery of the first and second signal wiring patterns 112 and 114 is open. Therefore, the electromagnetic field leaks to the side opposite to the substrate side of the first and second signal wiring patterns 112 and 114 and to both sides of the patterns 112 and 114.
[0004]
As is apparent with reference to FIG. 7B, the signal pattern current flows between the first signal wiring pattern 112 and the second signal wiring pattern 114 via the signal via 116. Here, considering the path of the return current (return path) of the signal pattern current, when a high-frequency current flows through the first signal wiring pattern 112, the return current is the ground layer 104 immediately below the first signal wiring pattern 112. Flowing. When a high frequency current flows through the second signal wiring pattern 114, the return current flows through the power supply layer 108 immediately above. However, when a current flows from the first signal wiring pattern 112 to the second signal wiring pattern 114 via the signal via 116, a return current path from the ground layer 104 to the power supply layer 108 is not secured. As a result, the return current having no place to go is widely distributed in the ground layer 104 or the power supply layer 108.
[0005]
Therefore, the leakage of the electromagnetic field and the return current that has been widely distributed become a radiation source, which may cause EMI. For this reason, conventionally, it has been necessary to take measures such as using noise countermeasure parts or providing an external shield.
[0006]
Therefore, the appearance of a wiring structure substrate that can reduce unnecessary radiation has been desired.
[0007]
[Means for Solving the Problems]
For this reason, the wiring structure substrate of the present invention is configured as described below. In the configuration described below, the first main surface and the second main surface of the substrate (wiring structure substrate) refer to either the front surface or the back surface of the substrate. For example, when the surface of the substrate is the first main surface, the back surface of the substrate is referred to as the second main surface. In the multilayer substrate, for example, when the uppermost surface is the first main surface, the lowermost surface is the second main surface.
[0008]
  Therefore, the wiring structure substrate of the present invention is a multilayer substrate on which electronic circuit components are mounted on the first main surface. The substrate includes a first insulating layer having a first main surface, a second insulating layer having a second main surface, a first signal wiring pattern,As a ground layerA first conductor layer, a second signal wiring pattern,As a power layerA second conductor layer, a signal via, a third conductor layer, a fourth conductor layer, a first via, and a second via are provided. The first signal wiring pattern is formed in an area other than the mounting area of the electronic circuit component on the first main surface of the substrate. The first conductor layer is formed on the opposite side of the first signal wiring pattern with the first insulating layer interposed therebetween. The second signal wiring pattern is formed on the second main surface. The second conductor layer is formed on the opposite side of the second signal wiring pattern across the second insulating layer. The signal via is provided through the substrate and electrically connects the first signal wiring pattern and the second signal wiring pattern. The third conductor layer is located on the first main surface of the substrate other than the electronic circuit component mounting region, and in the region other than the first signal wiring pattern forming region, the electronic circuit component and the first signal wiring pattern It is provided so as not to be electrically connected, that is, in an electrically disconnected state. The fourth conductor layer is provided in a region other than the second signal wiring pattern on the second main surface of the substrate in an electrically non-connected state with the second signal wiring pattern. The first via is provided through the first insulating layer for securing a return path, and electrically connects the second conductor layer and the third conductor layer. The second via is provided through the second insulating layer for securing a return path, and electrically connects the first conductor layer and the fourth conductor layer.
Further, the distance along the first main surface between the center of the signal via and the center of the first via for securing the return path, and the first main surface between the center of the signal via and the center of the second via for securing the return path. Distance is set equal.
Further, the first conductor layer is formed so as to cover the entire surface of the first insulating layer opposite to the first signal wiring pattern, and the second conductor layer is formed of the second insulating layer. The surface opposite to the two-signal wiring pattern is entirely covered.
[0009]
Since the wiring structure substrate having the above-described structure is provided with a conductor layer on the same surface as the surface on which the first and second signal wiring patterns are formed, this conductor layer acts as a shield. . That is, the distribution of the electromagnetic field from the signal wiring pattern can be suppressed by the conductor layer.
[0010]
The conductor layer may be provided along the direction in which the signal pattern current of the signal wiring pattern flows, and may be formed on one side of the signal wiring pattern, but it is preferable to form the conductor layer on both sides. The signal wiring pattern may be formed in a U-shape or an O-shape so as to surround the open end of the signal wiring pattern, or the signal wiring is formed around the signal wiring pattern in a state of being electrically disconnected from the signal wiring pattern. You may form over the whole surface in which the pattern is provided. The effect of suppressing the electromagnetic field distribution is higher when the distance between the conductor layer and the signal wiring pattern is as short as possible.
[0011]
Further, the third conductor layer provided on the first main surface is electrically connected to the second conductor layer through the first via for securing the return path. Similarly, the fourth conductor layer provided on the second main surface is electrically connected to the first conductor layer via the return path securing second via. Therefore, when a signal pattern current flows from the first signal wiring pattern to the second signal wiring pattern through the signal via, the return is made from the second conductor layer to the third conductor layer through the return path securing first via. Current flows. On the other hand, when a signal pattern current flows from the second signal wiring pattern to the first signal wiring pattern, a return current flows from the first conductor layer to the fourth conductor layer through the return securing second via. Accordingly, a return current path can be secured when a signal pattern current is passed between the first signal wiring pattern and the second signal wiring pattern via the signal via, so that the return current is a conductor layer in the substrate. Can be suppressed from being widely distributed. Therefore, unnecessary radiation from the wiring structure substrate can be suppressed. Further, it is not necessary to take measures such as providing a shield against unwanted radiation or using noise countermeasure parts. Therefore, the manufacturing cost of the wiring structure board can be reduced. For this reason, the effect of reducing the manufacturing cost of products such as information processing equipment using this substrate can also be expected.
[0012]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an embodiment of the present invention will be described with reference to the drawings. Each drawing merely schematically shows the shape, size, and arrangement relationship of each component so that the invention can be understood. Therefore, the present invention is not limited to the illustrated examples. Further, in the drawing, hatching (hatched lines) indicating a cross section is omitted except for a part for easy understanding of the drawing.
[0013]
FIG. 1 is a configuration diagram of a wiring structure substrate according to an embodiment of the present invention, and is shown in a perspective view. FIG. 2 is a cross-sectional view of the wiring structure substrate taken along a straight line passing through the center of the signal via in a direction orthogonal to the direction in which the wiring pattern current flows.
[0014]
First, the wiring structure substrate 10 of this embodiment is a multilayer substrate, and its surface 12 is referred to as a first main surface, and a surface (back surface) 14 opposite to the surface is referred to as a second main surface. Then, for example, an electronic circuit component is mounted on the first main surface 12 (not shown).
[0015]
The wiring structure substrate 10 includes a first insulating layer 16 having the first main surface 12 and a second insulating layer 18 having a second main surface 14. A first signal wiring pattern 20 is formed in a region other than the electronic component mounting region on the surface 12 of the first insulating layer 16 (first main surface of the substrate). A first conductor layer 22 is formed on the opposite side of the first insulating layer 16 from the first signal wiring pattern 20, that is, on the back surface of the first insulating layer 16.
[0016]
A second signal wiring pattern 24 is formed on the back surface (second main surface of the substrate) 14 of the second insulating layer 18. A second conductor layer 26 is formed on the opposite side of the second signal wiring pattern 24, that is, on the surface of the second insulating layer 18.
[0017]
Therefore, the layer configuration of the multilayer substrate 10 of this embodiment includes the second signal wiring pattern 24, the second insulating layer 18, the second conductor layer 26, the first conductor layer 22, and the first insulating layer 16 in order from the lower layer side. The first signal wiring pattern 20 is provided. An interlayer insulating layer 28 is formed between the second conductor layer 26 and the first conductor layer 22.
[0018]
A via 30 is formed through the multilayer substrate (also simply referred to as a substrate) 10, and the first signal wiring pattern 20 and the second signal wiring pattern 24 are electrically connected by the via 30. ing. Therefore, this via 30 is referred to as a signal via.
[0019]
In the wiring structure substrate 10 of this embodiment, the third conductor layer 32 is formed in a region other than the mounting region of the electronic circuit component on the first main surface 12 and the formation region of the first signal wiring pattern 20. Yes. The third conductor layer 32 is provided so as not to be electrically connected to the electronic circuit component and the first signal wiring pattern 20. Further, a fourth conductor layer 34 is formed in a region other than the second signal wiring pattern 24 on the second main surface 14. The fourth conductor layer 34 is provided so as not to be electrically connected to the second signal wiring pattern 24 (see FIG. 2).
[0020]
In this embodiment, the third conductor layer 32 is formed over the entire first main surface 12 except for the electronic circuit component mounting region and the first signal wiring pattern 20 formation region. And the 4th conductor layer 34 is also formed over the 2nd main surface 14 whole area other than the 2nd signal wiring pattern 24 formation area similarly to the 3rd conductor layer 32 (refer FIG. 1).
[0021]
In addition, a via 36 penetrating the first insulating layer 16 is formed. The via 36 electrically connects the second conductor layer 26 and the third conductor layer 32. Therefore, the via 36 is not electrically connected to the first conductor layer 22 between the second conductor layer 26 and the third conductor layer 32. This via 36 is referred to as a return path securing first via. Therefore, an opening 38 larger than the diameter of the first return path securing via 36 is formed in the first conductor layer 22 in the region where the first return path securing via 36 is formed (see FIG. 2). . The return path securing first via 36 is formed inside the opening 38.
[0022]
The second insulating layer 18 is also formed with a via 40 that penetrates the layer 18. The via 40 electrically connects the first conductor layer 22 and the fourth conductor layer 34. Therefore, the via 40 is not electrically connected to the second conductor layer 26 between the first conductor layer 22 and the fourth conductor layer 34. This via 40 is referred to as a return path securing second via. Therefore, an opening 42 larger than the diameter of the return path securing second via 40 is formed in the second conductor layer 26 in the region where the return path securing second via 40 is formed (see FIG. 2). . The return path securing second via 40 is formed inside the opening 42.
[0023]
Next, the behavior of the electromagnetic field around the signal wiring patterns 20 and 24 will be described by applying a high-frequency current to the signal wiring patterns 20 and 24 of the wiring structure substrate 10 having the above-described configuration.
[0024]
First, when a high-frequency current as a signal pattern current flows through the first signal wiring pattern 20, the return current causes the region of the first conductor layer 22 immediately below the first signal wiring pattern 20 to pass through the first signal wiring pattern 20. It flows in the direction opposite to the direction of the flowing current. At this time, the third conductor layer 32 formed on the entire surface 12 of the surface 12 of the first insulating layer 16 other than the first signal wiring pattern 20 formation region and the electronic circuit component mounting region is the first signal wiring pattern. Although it does not contact 20, it is formed in a region close to the pattern 20. Therefore, considering that the current flowing through the first signal wiring pattern 20 is a high-frequency current, the third conductor layer 32 is a layer having the same function as the ground layer, that is, the ground layer. Therefore, since the electromagnetic field around the first signal wiring pattern 20 is formed between the first signal wiring pattern 20 and the third conductor layer 32, it is possible to prevent the electromagnetic field from leaking to the outside.
[0025]
Next, when a high-frequency current flows from the first signal wiring pattern 20 to the second signal wiring pattern 24 via the signal via 30, the return current passes from the second conductor layer 26 to the return path securing first via 36. Then, it flows to the third conductor layer 32.
[0026]
Therefore, a return current path for the signal pattern current can be secured.
[0027]
Also, the return current can take another path. That is, this is a path that flows from the fourth conductor layer 34 to the first conductor layer 22 via the return path securing second via 40.
[0028]
For this reason, the possibility that the high-frequency current caused by the return current is widely distributed in the conductor layer in the substrate 10 can be reduced.
[0029]
Conversely, when a high-frequency current flows from the second signal wiring pattern 24 to the first signal wiring pattern 20 via the signal via 30, the return current is transmitted from the first conductor layer 22 to the return path securing second via 40. Flows to the fourth conductor layer 34.
[0030]
Again, another path of return current can be considered. That is, this is a path from the third conductor layer 32 to the second conductor layer 26 via the return path securing first via 36.
[0031]
Therefore, a return current path can be secured.
[0032]
Further, when a current flows through the second signal wiring pattern 24, the fourth conductor layer 34 formed in the vicinity of the second signal wiring pattern 24 has an electromagnetic field between the second signal wiring pattern 24 and the second signal wiring pattern 24. Form. Therefore, the possibility that the electromagnetic field formed around the second signal wiring pattern 24 spreads and leaks to the outside is reduced.
[0033]
As described above, according to the configuration of the present invention, the leakage of the electromagnetic field around the signal wiring pattern, which is a cause of unnecessary radiation, and the high-frequency current without a place due to the return current are generated in the conductor layer in the substrate 10. Therefore, unnecessary radiation from the substrate 10 can be greatly reduced.
[0034]
Therefore, since the generation of noise due to unnecessary radiation can be suppressed, noise countermeasure parts and shields are not necessary.
[0035]
Therefore, unnecessary radiation can be suppressed at a low cost, which leads to cost reduction of the substrate itself.
[0036]
【Example】
Hereinafter, the present invention will be described with more specific examples. In addition, numerical conditions, such as the material of the structural component used in the Example, the dimension of each part, are only examples of the structural example of this invention, Therefore, it is not limited to this.
[0037]
FIG. 3 is a schematic view showing the configuration of the wiring structure substrate of this embodiment, and is a plan view seen from above. FIG. 4 is a schematic cross-sectional view of a region around the signal wiring pattern.
[0038]
3 and 4, the same components as those in the above-described embodiment are denoted by the same reference numerals as those used in FIGS. 1 and 2.
[0039]
The wiring structure substrate 10 of this embodiment includes a first insulating layer 16 and a second insulating layer 18 each having a thickness of approximately 0.2 mm, and a first conductor layer 22 and a second conductor having a thickness of approximately 0.035 mm, respectively. A conductor layer 26 and an interlayer insulating layer 28 having a thickness of about 1.034 mm are provided.
[0040]
A first signal wiring pattern 20 having a thickness of about 0.043 mm is formed on the surface 12 of the first insulating layer 16, and a thickness of about 0.03 mm is also formed on the back surface 14 of the second insulating layer 18. A second signal wiring pattern 24 of 043 mm is formed.
[0041]
In this embodiment, the third signal having a thickness of 0.043 mm is provided so as not to be electrically connected to the first signal wiring pattern 20 in a region other than the first signal wiring pattern 20 on the surface 12 of the first insulating layer 16. A conductor layer 32 is formed.
[0042]
Further, a fourth conductor layer having a thickness of 0.043 mm is provided in a region other than the second signal wiring pattern 24 on the back surface 14 of the second insulating layer 18 so as not to be electrically connected to the second signal wiring pattern 24. 34 is formed (FIG. 4).
[0043]
Moreover, the 1st insulating layer 16, the 2nd insulating layer 18, and the interlayer insulation layer 28 are formed with the glass epoxy resin (FR-4). The first conductor layer 22 and the second conductor layer 26 are copper foil.
[0044]
The first and second signal wiring patterns 20, 24, the third conductor layer 32, and the fourth conductor layer 34 are made of copper foils 20a, 24a, 32a, 34a and plated layers 20b, 24b, A two-layer structure of 32b and 34b is adopted (FIG. 4).
[0045]
The first and second signal wiring patterns 20 and 24 are provided along the same arrangement line facing each other.
[0046]
The entire upper side of the first insulating layer 16 and the entire lower side of the second insulating layer are covered with a resist film 44 (FIG. 4).
[0047]
Also, as shown in FIG. 3, in this embodiment, six first signal wiring patterns 20 (20p, 20q, 20r, 20s, 20t, 20u) are formed in different directions.
[0048]
One end of these six signal wiring patterns 20 is connected to the driver IC 50.
[0049]
On the other hand, the other end of the signal wiring pattern 20 is open. The first signal wiring patterns 20q and 20t are provided so as to extend on the same straight line in opposite directions with the driver IC 50 as the center.
[0050]
The first signal wiring patterns 20p, 20r, 20s, and 20u are provided in a broken line state in which both end portions are straight lines parallel to each other and the central portion is an oblique straight line.
[0051]
These parallel straight portions and oblique straight portions intersect and are coupled at an obtuse angle.
[0052]
Further, the first signal wiring patterns 20u and 20s are arranged in contrast with 20t as a center line, and the first signal wiring patterns 20p and 20r are arranged in contrast with 20q as a center line. .
[0053]
The first signal wiring patterns are close to each other in the driver IC 50, but the open ends are greatly separated from each other.
[0054]
In this example, the six first signal wiring patterns 20 are connected to the second signal wiring patterns 24 (24q, 24r, 24s, 24t, 24u) by different numbers of signal vias 30, respectively.
[0055]
In the first pattern 20p, the number of signal vias is zero.
[0056]
The second pattern 20q is connected to the second pattern 24q of the second signal wiring pattern by eight signal vias 30.
[0057]
The third pattern 20r is connected to the third pattern 24r of the second signal wiring pattern by two signal vias 30.
[0058]
The fourth pattern 20 s is connected to the fourth pattern 24 s of the second signal wiring pattern by six signal vias 30.
[0059]
The fifth pattern 20t is connected to the fifth pattern 24t of the second signal wiring pattern by four signal vias 30.
[0060]
The sixth pattern 20u is connected to the sixth pattern 24u of the second signal wiring pattern by one signal via 30 (FIG. 3).
[0061]
The wiring widths of the first and second signal wiring patterns 20 and 24 are 0.18 mm.
[0062]
In this embodiment, return path securing first vias 36 and second vias 40 are formed in regions of the substrate 10 on both sides of each signal via 30 (see FIGS. 3 and 1).
[0063]
A straight line connecting the center position of the first via 36 and the center position of the second via 40 is a straight line passing through the center of the signal via 30 and is orthogonal to the first signal wiring pattern 20.
[0064]
The distance d1 from the center of the first via 36 to the center of the signal via 30 is the same as the distance d2 from the center of the second via 40 to the center of the signal via 30. In this example, distances d1 and d2 from the centers of the first and second vias to the center of the signal via are set to 1.5 mm. The signal via 30 and the return path securing via (first via 36 and second via 40) are both plated with copper on the inner wall, and the diameter of the plated via is 0.3 mm.
[0065]
The signal via 30 connects the first signal wiring pattern 20 and the second signal wiring pattern 24. Therefore, a copper land 52 continuous with the plated copper of the signal via 30 is formed in a ring shape on the surface 12 of the first insulating layer 16.
[0066]
Similarly, lands 52 are also formed on the back surface 14 of the second insulating layer 18. The land 52 and the first signal wiring pattern 20 or the second signal wiring pattern 24 are electrically connected (see FIGS. 1 and 2).
[0067]
The return path securing first via 36 is a via connecting the second conductor layer 26 and the third conductor layer 32.
[0068]
Accordingly, an opening 54 is formed around the first via 36 formation region of the fourth conductor layer 34 (see FIG. 2). The back surface 14 of the second insulating layer 18 is exposed from the opening 54. Further, a land 56 having a diameter of 0.7 mm outside the ring is formed around the hole for the first via 36, and the size of the opening 54 is larger than that of the land 56. Therefore, the land 56 and the fourth conductor layer 34 are not electrically connected (FIG. 2).
[0069]
The return path securing second via 40 is a via connecting the first conductor layer 16 and the fourth conductor layer 34.
[0070]
Accordingly, an opening 58 is formed around the second via 40 formation region of the third conductor layer 32. The surface 12 of the first insulating layer 16 is exposed from the opening 58.
[0071]
In addition, a land 60 having a diameter of 0.7 mm outside the ring is formed around the hole for the second via 40.
[0072]
The size of the opening 58 is larger than that of the land 60.
[0073]
Therefore, the land 60 and the third conductor layer 32 are not electrically connected.
[0074]
The external dimensions of the wiring structure substrate 10 are 149.86 mm × 231.14 mm.
[0075]
A driver IC 50 is mounted on the surface 12 of the first insulating layer 16 of the substrate 10 (FIG. 3). In this example, a standard logic IC 74ALVC04 (for example, manufactured by TI (Texas Instruments)) is used as a driver.
[0076]
Although not shown, a 50 MHz clock and a battery-driven power source are mounted on the back side of the substrate 10, and these are covered with a shield box. For this reason, the influence of electromagnetic waves by these components does not reach the periphery of the signal wiring patterns 20 and 24.
[0077]
Thereby, the wiring structure substrate 10 which is a specific configuration example of the present invention is obtained.
[0078]
Next, unnecessary radiation from the wiring structure substrate 10 described with reference to FIGS. 3 and 4 is measured.
[0079]
Therefore, the first conductor layer 16 and the fourth conductor layer 34 of the wiring structure substrate 10 are used as ground layers, and the second conductor layer 18 and the third conductor layer 32 are used as power supply layers.
[0080]
Here, the measurement is performed by a spectrum analyzer using an anechoic chamber 3m method that complies with the standards of VCCI (Voluntary Control Council for Interference by Information Technology Equipment). Then, the horizontal polarization when the antenna is mounted in the horizontal direction and the vertical polarization when it is set in the vertical direction are measured.
[0081]
The antenna height is measured from 1 m to 4 m, and the maximum value is obtained. The frequency range is 30 MHz to 1000 MHz.
[0082]
The measurement results are shown in FIGS. 5 (A) and 5 (B). FIG. 5A is a characteristic diagram of horizontal polarization change caused by unnecessary radiation with respect to frequency change. FIG. 5B is a change characteristic diagram of vertical polarization caused by unnecessary radiation with respect to frequency change.
[0083]
5A and 5B both show the frequency (MHz) on the horizontal axis and the radiation intensity (dB (μV / m)) on the vertical axis.
[0084]
Moreover, in FIG. 5, it measures for every frequency 50MHz, The peak value is shown. The curve between the peaks is an antenna factor, and is corrected according to the frequency characteristics of the antenna.
[0085]
Here, as a comparative example, FIGS. 6A and 6B show measurement results of unnecessary radiation of the conventional wiring structure substrate. The structure of the wiring structure substrate of the comparative example is the same as the structure of the example, the third conductor layer 32 provided on the first insulating layer 16, the fourth conductor layer 34 provided on the back surface 14 of the second insulating film 18, The first pass 36 and the second via 40 for securing the return path are excluded.
[0086]
According to FIGS. 5 (A) and 5 (B), unnecessary radiation from the wiring structure substrate 10 of this embodiment is almost the same in both horizontal polarization and vertical polarization within the frequency range of 30 MHz to 1000 MHz. It could be suppressed to 40 dB or less.
[0087]
Further, according to FIGS. 6 (A) and 6 (B), high unnecessary radiation has been measured from the conventional substrate as the frequency is increased, and in horizontal polarization, it is 46 dB at 950 MHz. Intense unwanted radiation was measured. In the vertical polarization, high unnecessary radiation around 58 dB was measured at a frequency of 655 MHz.
[0088]
Therefore, by providing the third conductor layer 32 and the fourth conductor layer 34 on the first main surface 12 and the second main surface 14 of the substrate 10, they are formed on the same first main surface 12 and second main surface 14. When a high frequency current flows through the signal wiring patterns 20 and 24, leakage of electromagnetic fields from the signal wiring patterns 20 and 24 can be suppressed. Thereby, one of the causes of unnecessary radiation can be eliminated.
[0089]
The return path securing first via 36 connecting the second conductor layer 26 and the third conductor layer 32 and the return path securing second via 40 connecting the first conductor layer 22 and the fourth conductor layer 34. Are provided close to the signal via 30, so that when the signal pattern current flows between the first signal wiring pattern 20 and the second signal wiring pattern 24 via the signal via 30, the return current of A route can be secured.
[0090]
Therefore, the situation where the return current is lost is eliminated, so that the high-frequency current can be prevented from being widely distributed to the conductor layer in the substrate 10.
[0091]
If d1 and d2 are too long, the distribution range of the electromagnetic field from the return current may be expanded. Specifically, d1 and d2 are preferably shorter within a range of about 2 mm or less. Thereby, another cause of unnecessary radiation can be eliminated.
[0092]
Therefore, it is possible to provide a wiring structure substrate in which generation of unnecessary radiation is suppressed as compared with the conventional case. Further, since it is not necessary to use noise countermeasure parts, shields, or the like for suppressing unnecessary radiation, a more inexpensive wiring structure board can be provided.
[0093]
The wiring structure substrate of the present invention can be applied to a general digital circuit substrate. Therefore, the substrate of the present invention is suitable for application to all products that use digital circuits, such as information processing equipment.
[0094]
In the above-described embodiment, the example in which the interlayer insulating layer is interposed between the first conductor layer and the second conductor layer has been described. However, the present invention is not limited to this, and the first conductor layer and the second conductor layer There may be a plurality of other conductor layers interposed between the insulating layers.
[0095]
At this time, the signal via is a via that connects only the first signal wiring pattern and the second signal wiring pattern, and is electrically disconnected from the plurality of interposed conductor layers.
[0096]
【The invention's effect】
As is apparent from the above description, according to the wiring structure substrate of the present invention, the conductor layer provided around the first and second signal wiring patterns acts like a shield, The distribution of the electromagnetic field can be suppressed.
[0097]
Further, the third conductor layer provided on the first main surface is electrically connected to the second conductor layer through the first via for securing the return path. Similarly, the fourth conductor layer provided on the second main surface is electrically connected to the first conductor layer via the return path securing second via. Therefore, when a signal pattern current flows from the first signal wiring pattern to the second signal wiring pattern through the signal via, the return is made from the second conductor layer to the third conductor layer through the return path securing first via. Current flows. On the other hand, when a signal pattern current flows from the second signal wiring pattern to the first signal wiring pattern, a return current flows from the first conductor layer to the fourth conductor layer through the return securing second via.
[0098]
Accordingly, a return current path can be secured when a signal pattern current is passed between the first signal wiring pattern and the second signal wiring pattern via the signal via, so that the return current is a conductor layer in the substrate. Can be suppressed from being widely distributed.
[0099]
Therefore, unnecessary radiation from the wiring structure substrate can be suppressed.
[0100]
Further, it is not necessary to take measures such as providing a shield against unwanted radiation or using noise countermeasure parts.
[0101]
Therefore, the manufacturing cost of the wiring structure board can be reduced.
[0102]
For this reason, the effect of reducing the manufacturing cost of products such as information processing equipment using this substrate can also be expected.
[Brief description of the drawings]
FIG. 1 is a perspective view showing a schematic configuration of a wiring structure substrate according to the present invention.
FIG. 2 is a cross-sectional view showing a schematic configuration of a wiring structure substrate according to the present invention.
FIG. 3 is a plan view of the wiring structure substrate as viewed from above for explaining the embodiment;
FIG. 4 is a cross-sectional view of a wiring structure substrate for explaining an embodiment.
FIG. 5 is a characteristic diagram showing measurement results of unnecessary radiation intensity from a wiring structure substrate for explaining the embodiment, wherein (A) is a measurement result of unnecessary radiation intensity of horizontal polarization; ) Is a measurement result of unnecessary radiation intensity of vertical polarization.
FIG. 6 is a characteristic diagram showing a measurement result of unnecessary radiation intensity from a conventional wiring structure substrate as a comparative example, where (A) is a measurement result of unwanted radiation intensity of horizontal polarization; ) Is a measurement result of unnecessary radiation intensity of vertical polarization.
7A is a perspective view showing a schematic configuration of a conventional wiring structure substrate, and FIG. 7B is a cross-sectional view.
[Explanation of symbols]
10: Wiring structure substrate (multilayer substrate, substrate)
12: Surface (first main surface)
14: Back surface (second main surface)
16, 102: First insulating layer
18, 110: second insulating layer
20, 112: first signal wiring pattern
20a, 24a, 32a, 34a: copper foil
20b, 24b, 32b, 34b: plating layer
20p, 24p: 1st pattern
20q, 24q: second pattern
20r, 24r: third pattern
20s, 24s: 4th pattern
20t, 24t: 5th pattern
20u, 24u: 6th pattern
22: First conductor layer
24, 114: second signal wiring pattern
26: Second conductor layer
28, 106: Interlayer insulating layer
30, 116: Via (signal via)
32: Third conductor layer
34: Fourth conductor layer
36: Via (first via for securing return path, first via)
38, 42, 54, 58: Opening
40: Via (second via for securing return path, second via)
44: Resist film
50: Driver IC
52, 56, 60: Land
104: Ground layer
108: Power supply layer

Claims (5)

In a multilayer wiring structure board on which electronic circuit components are mounted on the first main surface,
A first insulating layer having the first main surface;
A second insulating layer having a second main surface opposite to the first main surface of the substrate;
A first signal wiring pattern formed in a region other than the mounting region of the electronic circuit component on the first main surface;
A first conductor layer as a ground layer formed on a surface of the first insulating layer opposite to the first signal wiring pattern;
A second signal wiring pattern formed on the second main surface;
A second conductor layer as a power supply layer formed on a surface of the second insulating layer opposite to the second signal wiring pattern;
A signal via that is provided through the substrate and electrically connects the first signal wiring pattern and the second signal wiring pattern;
The electronic circuit component and the first signal wiring pattern, which are provided in a region other than the mounting area of the electronic circuit component and the first signal wiring pattern formation region on the first main surface, are electrically disconnected from the first main surface. Three conductor layers;
A fourth conductor layer provided in a region other than the second signal wiring pattern on the second main surface and electrically unconnected to the second signal wiring pattern;
A first via for securing a return path provided through the first insulating layer and electrically connecting the second conductor layer and the third conductor layer;
The second provided through the insulating layer, and e ingredients and a second for a via return path ensures that electrically connect the fourth conductive layer and the first conductor layer,
The distance along the first main surface between the center of the signal via and the center of the first via for securing the return path, and the first between the center of the signal via and the center of the second via for securing the return path. The distance along the main surface is equal,
The first conductor layer is formed so as to cover the entire surface of the first insulating layer opposite to the first signal wiring pattern.
The wiring structure substrate, wherein the second conductor layer is formed so as to cover the entire surface of the second insulating layer opposite to the second signal wiring pattern . The wiring structure board according to claim 1,
The first via and the second via are:
Each wiring structure board is provided close to the signal via. In the wiring structure board according to claim 1 or 2,
The third conductor layer is provided along the first signal wiring pattern,
The wiring structure substrate, wherein the fourth conductor layer is provided along the second signal wiring pattern. The wiring structure board according to any one of claims 1 to 3,
The third conductor layer is formed over the entire region of the first main surface other than the mounting region and the first signal wiring pattern formation region,
The wiring structure substrate, wherein the fourth conductor layer is formed over the entire region of the second main surface other than the second signal wiring pattern formation region. In the wiring structure board according to any one of claims 1 to 4,
A wiring structure substrate, wherein an interlayer insulating layer is provided between the first conductor layer and the second conductor layer.

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