JPS6024088A - Method of producing testing printed board - Google Patents

Method of producing testing printed board

Info

Publication number
JPS6024088A
JPS6024088A JP13205083A JP13205083A JPS6024088A JP S6024088 A JPS6024088 A JP S6024088A JP 13205083 A JP13205083 A JP 13205083A JP 13205083 A JP13205083 A JP 13205083A JP S6024088 A JPS6024088 A JP S6024088A
Authority
JP
Japan
Prior art keywords
board
lands
holes
printed circuit
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13205083A
Other languages
Japanese (ja)
Inventor
昭夫 麦島
保 杉本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SHIRAI DENSHI KOGYO KK
Original Assignee
SHIRAI DENSHI KOGYO KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SHIRAI DENSHI KOGYO KK filed Critical SHIRAI DENSHI KOGYO KK
Priority to JP13205083A priority Critical patent/JPS6024088A/en
Publication of JPS6024088A publication Critical patent/JPS6024088A/en
Pending legal-status Critical Current

Links

Landscapes

  • Structure Of Printed Boards (AREA)
  • Manufacturing Of Printed Circuit Boards (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 本発明は試作、試験用プリント基板の製造方法に関する
ものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a printed circuit board for trial production and testing.

試作、試験用プリント基板としては、従来基本格子上に
穴明ランドを形成したユニバーサル基板が用いられてい
るプリント基板上に工C等の電子部品友実装してその配
置及び通電の試験を行ったり、図面上で画かれた回路が
実際に有効かどうかを試作してみるためには、このユニ
バーサル基板を使用する。
As a printed circuit board for prototyping and testing, electronic components such as engineering C are mounted on a printed circuit board, which conventionally uses a universal board with perforated lands formed on a basic grid, and their placement and energization tests are carried out. This universal board is used to test whether the circuit drawn on the drawing is actually effective.

即チ、ユニバーサル基板のランドに部品を取υ付け、ラ
ンドとランド間及び部品の端子と端子間をワイヤーで配
線するものである。また、他の方法としては、使用頻度
の高い電源線などを、予めパターン形成したユニバーサ
ル基板に部品を取シつけ、それら部品端子間やランド間
をワイヤー配線する方法が採られている。
In other words, components are mounted on the lands of the universal board, and wires are used between the lands and between the terminals of the components. Another method is to mount components onto a universal board on which frequently used power lines and the like are patterned in advance, and then wire wires between terminals of the components or between lands.

これら従来の試作、試験用プリント基板は、次の如き数
多くの欠点を有しているものである。
These conventional prototype and test printed circuit boards have many drawbacks as follows.

即ち、部品の端子と端子間をワイヤーで配線結線するた
め製造に極めて手数を要し、時間的にもかなυ長時間を
かける必要がある。さらに、手作業による配線であシ、
部品やランド間を複雑に交叉させて配線するため′その
仕上りの信頼性に問題があシ、シばしば誤配線を招いて
いる。さらに、ワイヤーによる空間配線を行っているた
め、試作後通電試験を行って、実際のプリント配線をし
た場合、ワイヤーの空間配線損失とプリント配線の抵抗
の相違などから正確な通電量が得られないことが多かっ
た。
That is, since the terminals of the parts are connected with wires, manufacturing is extremely labor-intensive and requires a considerable amount of time. In addition, manual wiring is required,
Because the wiring is complicated and intersects between parts and lands, there are problems with the reliability of the finish, often leading to incorrect wiring. Furthermore, since space wiring is performed using wires, when conducting a current conduction test after prototyping and then performing actual printed wiring, an accurate amount of current cannot be obtained due to differences in the space wiring loss of the wires and the resistance of the printed wiring. There were many things.

本発明はこれら従来の試作、試験用プリント基板の有す
る欠点をすべて解消し7、半期間で信頼性あるプリント
基板を製作し得る試作、試験用プリント基板の叛造方法
を提供するものである。
The present invention eliminates all the drawbacks of the conventional printed circuit boards for prototyping and testing, and provides a method for fabricating printed circuit boards for prototyping and testing that can produce reliable printed circuit boards in half a period of time.

即ち本発明は、銅張積層板の基本格子上を穿孔し、線入
をスルーホールメッキ1−て基準基板を作成し、該基板
上に回路構成フィルム及び穴部連結線構成フィルムによ
り必要回路のフォトレジストを形成して後、この基準基
板をエツチング処理することKおり不必要ヌル−ホール
及び不必要銅箔面を除去し、必要部分の大面周囲には迂
回連絡線を残存させた回路を構成することを特徴とする
試作、試験用プリント基板の製造方法である。
That is, the present invention creates a reference board by drilling holes on the basic lattice of a copper-clad laminate and plating wires through the holes, and then forming necessary circuits on the board using a circuit construction film and a hole connection wire construction film. After forming the photoresist, this reference board is etched to remove unnecessary null holes and unnecessary copper foil surfaces, and to create a circuit with detour connecting lines remaining around the large area of the necessary parts. This is a method for manufacturing a printed circuit board for trial production and testing, characterized by comprising:

以下本発明の実施例について詳述する。Examples of the present invention will be described in detail below.

銅張積層板上で2.5411111の格子上を穿孔して
規則的な穴を有する基板を作成し、この穴に銅メッキを
行う。次に端部にコネクタ一部を従来法で形成し、適宜
形状の外形加工を行う。こうして作成した基板をユニバ
ーサル基板として用いる。
A board having regular holes is created by drilling holes on a 2.5411111 grid on a copper-clad laminate, and the holes are plated with copper. Next, a part of the connector is formed at the end using a conventional method, and an appropriate external shape is processed. The substrate thus created is used as a universal substrate.

このユニバーサル基板上に穴部連結線構成フィルムと回
路構成フィルムを用いてフォトレジストを形成する。穴
部連結線構成フ4/VJ、は、2.511肩の基本格子
上に格子の中心点のみをくシ抜いたドーナソツ型のラン
ド配置フィルムを用いる。この穴部連結線構成フィルム
と通常の回rI!r構成フィルムを重ねてユニバーサル
拷板上に焼付又は印刷してレジスト層を形成する。回路
構成フィルムは、部品挿通ランドや表裏導通の必要ある
ランド部分の銅付着を除去しないようにラン1:の中・
し点をつぶしてレジスト層を形成するよう構成されてい
る。
A photoresist is formed on this universal substrate using the hole connection line forming film and the circuit forming film. The hole connecting line configuration F4/VJ uses a donut-shaped land arrangement film in which only the center point of the grid is punched out on the basic grid of 2.511 shoulders. This hole connection line configuration film and normal rotation rI! A resist layer is formed by overlapping the r-component films and baking or printing them on a universal printing plate. The circuit configuration film should be placed in the middle of run 1 to avoid removing copper adhesion on parts insertion lands and lands where front and back conduction is required.
The resist layer is formed by crushing the dots.

レジスト層を形成した基板をエツチング処理すれば、必
要回路とともに、部品挿通ランド及び表裏導通の必要あ
るランドはスルーホールメッキのされたまkのランドが
得られ、逆に表裏導通すると不都合なランドは、片面の
みでランド間が結線される如く、ランドの周囲処迂回す
る迂回連絡線のみが残存し、それらランドのスルーホー
ル部はメッキが除去される。
By etching the board on which the resist layer has been formed, lands with through-hole plating are obtained for parts insertion lands and lands that require front and back conductivity, as well as necessary circuits.On the other hand, lands that are inconvenient to have front and back conductivity can be obtained. Only the connecting lines around the lands remain so that the lands are connected only on one side, and the plating is removed from the through-hole portions of these lands.

こうして製造されたプリント基板は図面に示す通電のも
のとなる。即ち、プリント基板1の一側辺にはコネクタ
一部2が形成され、基板1上には無数の規則的なスルー
ホールが現存する。基板1」二には表裏導通ランド3と
迂回連絡線ランド4が形成され、これら全体で回路が構
成される。表裏導通ランド3は、部品挿通や、表裏に電
気的連絡をする必要のある箇所に残存させるものであり
、迂回連絡線ランド4は、片面上のみで電気的連絡を必
要とする箇所に形成するものである3、これら両ランド
の断面は第3図及び第4図に示す如く、表裏導通ランド
乙の場合はスルーホール面に銅6が現出し、基板5の内
面の銅6と表面の回路用銅6とが導通されているのに対
し、迂回連絡線ランド4の場合は、スルーホール面に基
板5面が現出し、表裏に付着している回路用銅6とは絶
縁されている。迂回連絡線ランド4はその表面において
はヌル−ホールを取りまくドーナッツ形状で連絡線を形
成している。
The printed circuit board manufactured in this manner becomes energized as shown in the drawing. That is, a connector part 2 is formed on one side of a printed circuit board 1, and numerous regular through holes are present on the board 1. Front and back conductive lands 3 and detour connecting land 4 are formed on the substrate 1''2, and a circuit is formed by these as a whole. The front and back conductive lands 3 are left in places where parts need to be inserted and electrical connections between the front and back sides are required, and the detour connecting land 4 is formed in places where electrical connections are required only on one side. 3. The cross sections of these two lands are shown in Figures 3 and 4. In the case of front and back conductive lands, copper 6 appears on the through-hole surface, and the copper 6 on the inner surface of the board 5 and the circuit on the surface In contrast, in the case of the detour connecting line land 4, the surface of the board 5 is exposed on the through-hole surface and is insulated from the circuit copper 6 attached to the front and back surfaces. The detour connecting line land 4 forms a donut-shaped connecting line surrounding the null hole on its surface.

本発明の方法によれば、ユニバーサル基板を利用して試
作、試験用プリント基板を得るに際し、必要回路に添っ
て表裏導通ランドと表面のみの連絡線を形成する迂回連
絡線ランドの二種類のランドを選択的に基板上に構成す
るものである。従って、プリント基板上の指定位置に部
品を装着するだけで通電試験や位置ぎめ試作が可能とな
る。この結果、従来の如くワイヤー配線が全く不要で、
しかもワイヤー配線において生じる誤配線や、通電の信
頼性不良という問題がすべて解消される。
According to the method of the present invention, when obtaining a printed circuit board for prototyping or testing using a universal board, two types of lands are used: a front and back conductive land and a detour connecting land that forms a connecting line only on the surface along the required circuit. is selectively formed on the substrate. Therefore, it becomes possible to carry out energization tests and positioning prototypes simply by mounting components at designated positions on the printed circuit board. As a result, there is no need for wire wiring as in the past.
Moreover, problems such as incorrect wiring and poor reliability of current supply that occur in wire wiring are all eliminated.

サラに、従来ユニバーサル基板上でワイヤー配線してい
たものが、試作から生産まで10日間程度の日数を要し
ていたのにくらべ、本方法によれば1日で試作、生産可
能な態勢を採ることができ極めて実用価値の高いもので
ある。
Compared to conventional wire wiring on a universal board, which required about 10 days from prototyping to production, this method allows prototyping and production in one day. It has extremely high practical value.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明によって得られたプリント基板の斜視図
、第2図は第1図のA部分拡大平面図、第3図は第2図
のY−Y線断面図、第4図は同X−X線断面図である。 1、プリント基板 2、コネクタ一部 31、表裏導通ランド 4、迂回連絡線ランド5、基 
材 6、銅 特許出願人 シライ電子工業株式会社
FIG. 1 is a perspective view of a printed circuit board obtained by the present invention, FIG. 2 is an enlarged plan view of part A in FIG. It is a sectional view taken along the line X-X. 1, Printed circuit board 2, Connector part 31, Front and back conductive lands 4, Detour connecting line land 5, Base
Material 6. Copper patent applicant Shirai Electronics Industry Co., Ltd.

Claims (1)

【特許請求の範囲】[Claims] 1) 銅張積層板の基本格子上を穿孔し、線入をスルー
ホールメッキして基準基板を作成し、該基板上に回路構
成フィルム及び穴部連結線構成フィルムにより必要回路
のフォトレジストを形成して後、この標準基板をエツチ
ング処理することによシネ必要ヌル−ホーp及び不必要
銅箔面を除去し、必要部分の大面周囲には迂回連絡線を
残存させた回路を構成することを特徴とする試験用プリ
ント基板の製造方法。
1) Create a reference board by drilling holes on the basic lattice of the copper-clad laminate and plating the wires through the holes, and forming a photoresist for the necessary circuit on the board using a circuit configuration film and a hole connection line configuration film. After that, this standard board is etched to remove the necessary cine null holes and unnecessary copper foil surfaces, and to construct a circuit with detour connecting lines remaining around the large area of the necessary parts. A method for manufacturing a printed circuit board for testing, characterized by:
JP13205083A 1983-07-19 1983-07-19 Method of producing testing printed board Pending JPS6024088A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13205083A JPS6024088A (en) 1983-07-19 1983-07-19 Method of producing testing printed board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13205083A JPS6024088A (en) 1983-07-19 1983-07-19 Method of producing testing printed board

Publications (1)

Publication Number Publication Date
JPS6024088A true JPS6024088A (en) 1985-02-06

Family

ID=15072348

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13205083A Pending JPS6024088A (en) 1983-07-19 1983-07-19 Method of producing testing printed board

Country Status (1)

Country Link
JP (1) JPS6024088A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6263956U (en) * 1985-10-12 1987-04-21
JP2003507900A (en) * 1999-08-25 2003-02-25 クゥアルコム・インコーポレイテッド Bidirectional interface tool for printed wiring board development

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6263956U (en) * 1985-10-12 1987-04-21
JP2003507900A (en) * 1999-08-25 2003-02-25 クゥアルコム・インコーポレイテッド Bidirectional interface tool for printed wiring board development

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