DE2951055A1 - Terminalsystem - Google Patents

Terminalsystem

Info

Publication number
DE2951055A1
DE2951055A1 DE19792951055 DE2951055A DE2951055A1 DE 2951055 A1 DE2951055 A1 DE 2951055A1 DE 19792951055 DE19792951055 DE 19792951055 DE 2951055 A DE2951055 A DE 2951055A DE 2951055 A1 DE2951055 A1 DE 2951055A1
Authority
DE
Germany
Prior art keywords
dma
peripheral
signal
subsystem
system bus
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
DE19792951055
Other languages
German (de)
English (en)
Other versions
DE2951055C2 (enrdf_load_stackoverflow
Inventor
Minoru Inoshita
Gerald N Winfrey
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Bull HN Information Systems Inc
Original Assignee
Honeywell Information Systems Italia SpA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Honeywell Information Systems Italia SpA filed Critical Honeywell Information Systems Italia SpA
Publication of DE2951055A1 publication Critical patent/DE2951055A1/de
Application granted granted Critical
Publication of DE2951055C2 publication Critical patent/DE2951055C2/de
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G06F13/30—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal with priority control

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
DE19792951055 1978-12-26 1979-12-19 Terminalsystem Granted DE2951055A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US97319678A 1978-12-26 1978-12-26

Publications (2)

Publication Number Publication Date
DE2951055A1 true DE2951055A1 (de) 1980-07-17
DE2951055C2 DE2951055C2 (enrdf_load_stackoverflow) 1990-08-30

Family

ID=25520615

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19792951055 Granted DE2951055A1 (de) 1978-12-26 1979-12-19 Terminalsystem

Country Status (7)

Country Link
JP (1) JPS5588121A (enrdf_load_stackoverflow)
AU (1) AU534761B2 (enrdf_load_stackoverflow)
CA (1) CA1132265A (enrdf_load_stackoverflow)
DE (1) DE2951055A1 (enrdf_load_stackoverflow)
FR (1) FR2445556B1 (enrdf_load_stackoverflow)
GB (1) GB2039105B (enrdf_load_stackoverflow)
YU (1) YU40587B (enrdf_load_stackoverflow)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3431938A1 (de) 1983-08-30 1985-03-14 Canon K.K., Tokio/Tokyo Bildverarbeitungssystem

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5241661A (en) * 1987-03-27 1993-08-31 International Business Machines Corporation DMA access arbitration device in which CPU can arbitrate on behalf of attachment having no arbiter
US4901234A (en) * 1987-03-27 1990-02-13 International Business Machines Corporation Computer system having programmable DMA control
JP2550496B2 (ja) * 1989-03-30 1996-11-06 三菱電機株式会社 Ｄｍａコントローラ
RU2109327C1 (ru) * 1996-08-19 1998-04-20 Тульский государственный университет Многоканальное устройство приоритета

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3553656A (en) * 1969-06-03 1971-01-05 Gen Electric Selector for the dynamic assignment of priority on a periodic basis

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL154023B (nl) * 1969-02-01 1977-07-15 Philips Nv Prioriteitscircuit.
JPS5147298B2 (enrdf_load_stackoverflow) * 1971-08-30 1976-12-14
US3961312A (en) * 1974-07-15 1976-06-01 International Business Machines Corporation Cycle interleaving during burst mode operation

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3553656A (en) * 1969-06-03 1971-01-05 Gen Electric Selector for the dynamic assignment of priority on a periodic basis

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
DIEHL, Werner, Mikroprozessoren und Mikrocomputer,Vogel-Verlag, Würzburg, 1977, S. 106-120 *
NISSIN, Joseph, DMA Controler Capitalizes on Clock Cycles to Bypass CPV, In: Commputer Design, Januar 1978, S. 117-124 *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3431938A1 (de) 1983-08-30 1985-03-14 Canon K.K., Tokio/Tokyo Bildverarbeitungssystem

Also Published As

Publication number Publication date
JPS5588121A (en) 1980-07-03
GB2039105A (en) 1980-07-30
AU534761B2 (en) 1984-02-16
YU40587B (en) 1986-02-28
YU316779A (en) 1982-06-30
FR2445556A1 (fr) 1980-07-25
CA1132265A (en) 1982-09-21
DE2951055C2 (enrdf_load_stackoverflow) 1990-08-30
FR2445556B1 (fr) 1988-03-18
GB2039105B (en) 1983-02-16
JPS636891B2 (enrdf_load_stackoverflow) 1988-02-12
AU5300679A (en) 1980-07-03

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Legal Events

Date Code Title Description
8110 Request for examination paragraph 44
8127 New person/name/address of the applicant

Owner name: HONEYWELL BULL INC., MINNEAPOLIS, MINN., US

D2 Grant after examination
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee