GB2039105A - Multi-unit computer priority system - Google Patents

Abstract

A CPU 4, memory 10, and several peripheral units 12, 14a-22a, 14b-22b, etc., are coupled to a system bus 16-18. Bus cycles are assigned alternately to the CPU and the peripherals, and a revolving priority network 6 assigns the peripheral cycles cyclically to 4 chains 1 to 4, by signals DMA10 to DMA40. Chain 1 is a CRT subsystem 12. Each other chain includes several peripherals, e.g. 14a-22a, with the DMA signal passing through the chain until it reaches a unit wanting bus access; that unit thereupon accesses the bus and does not pass the DMA signal on down the chain. Each of chains 2 to 4 has a request line DMAREQ-02, etc., energized on a unit requesting access. This may be coupled to other units in the chain, so preventing them from requesting access, and if coupled to the same unit, preventing it from requesting access on 2 successive cycles. <IMAGE>

Description

SPECIFICATION Multi-unit computer priority system This invention relates generally to data processing systems with a number of units which may compete for access to a common bus or memory.

Systems having a central processor (CPU), a memory subsystem and a number of peripherals are well known. One method of controlling the system is by having the CPU, under program operation, control the peripheral input/output communication with memory through the CPU. This type of operation is satisfactory for low speed peripherals or for dedicated applications. This type of operation is not satisfactory for peripherals with high speed input/output requirements with memory.

To solve this problem systems were designed whereby the high performance peripherals communicated with memory without the intervention of the CPU. The CPU communicated with memory on CPU cycles and the peripherals communicated with memory during Direct Memory Access (DMA) cycles with the peripherals stealing CPU cycles to communicate with memory. This system had the disadvantage of reducing system throughput in an application where the high performance peripheral prevented CPU cycles.

To solve this problem, systems with dedicated CPU channels and DMA channels were designed. This had the problem that peripheral l/O throughput could be reduced by having high priority peripherals hogging the DMA cycles thereby preventing low priority peripherals from accessing memory. This problem is somewhat alleviated by a system wherein user devices are selectively assigned highest priority depending upon the last device granted access. This however still has the problem of the device assigned highest priority hogging the memory bus.

These problems were eased somewhat by a system having CPU cycles and DMA cycles.

CPU cycles are stolen by the DMA devices; however, the CPU can interrupt the DMA cycle. Also, a DMA control has eight DMA request/acknowledge lines to provide bidirectional control between the peripherals and the DMA controller. Each DMA line has a fixed priority. Each channel has a register to store the data length of the peripheral accessing the channel. The device relinquishes the channel when (a) the register has counted down to zero, (b) a request from a peripheral on a higher priority channel is received by the DMA controller, or (c) the CPU requests a CPU cycles.

This solution requires considerable DMA logic and "housekeeping", and retains some of the reduced throughput problems of the CPU cycle stealing systems discussed above and still has the problem of high priority peripherals hogging the bus.

Accordingly, it is an object of this invention to provide a priority system with improved throughput.

According to the invention there is provided a multi-unit computer priority system, com prising:- a a common bus to which all units may require access; a revolving priority network which produces a plurality of bus access control signals in cyclic sequence; and a plurality of units connected together in chains corresponding to the bus access control signals, each bus access control signal being applied to the first unit in the corresponding chain and passing through each unit not requiring bus access, and any unit requiring bus access achieving such access on receiving a bus access control signal and not passing the signal on down the chain.

A multi-unit computer system embodying the invention will now be described, by way of example, with reference to the accompanying drawings, in which: Figure 1 shows the system bus timing cycles.

Figure 2 is a block diagram of the system.

Figure 3 is a detailed logic diagram of the priority apparatus.

Figure 4 is a timing diagram of the Direct Memory Access priority logic interacting with system bus signals.

INTRODUCTORY SUMMARY A central processor subsystem, a memory subsystem and a plurality of peripheral subsystems are all connected in common to a system bus. The memory is available to the central processor subsystem and to the peripheral subsystems on alternate bus cycles.

The central processor subsystem is operative with memory during Central Processor Unit (CPU) system bus cycles and the peripheral subsystems are operative with memory during Direct Memory Access (DMA) system bus cycles. The successive DMA bus cycles, DMA1, DAM2, DMA3 and DMA4 occur cyclically and are assigned to specific peripheral subsystems. A cathode ray tube display is wired to be operative during the DMA1 bus cycle. The remainder of the peripheral subsystems are selectively wired to be operative on bus cycles DMA2, DMA3 or DMA4.

A terminal system with the revolving DMA channel can be configured to give a balanced peripheral subsystem, memory subsystem throughput. A device requiring a large amount of data from the memory subsystem may have the exclusive use of a DMA channel. In the preferred embodiment, the cathode ray tube has the exclusive use of the DMA1 bus cycle.

A A plurality of peripheral subsystems as signed to a particular DMA bus cycle, for example DMA2, have their priority logic wired to chain the subsystems. Thus two peripheral subsystems may be chained in the DMA2 channel and have, if required, alternate access during the DMA2 bus cycle.

A plurality of peripheral subsystems may be chained in the DMA3 channel with the peripheral subsystem closest to the system bus having top priority and the peripheral subsystem at the other end of the chain having lowest priority in access to the DMA3 bus cycle.

Also, a high performance peripheral subsystem may be connected to the DMA4 system bus with a plurality of very low performance peripheral subsystems chained with it. The high performance peripheral may be wired to hog the DMA4 bus cycle since it may operate in a burst mode. The activity would not be so great as to prevent the lower performance peripheral subsystems' access to the DMA4 bus cycle.

The system bus includes an address bus, a data bus and a control bus. The control bus includes signal lines associated with each DMA cycle. Each peripheral subsystem is operative during a selected DMA cycle be being connected to a particular control bus signal line identifying that DMA cycle. In one mode of operation, logic in each peripheral subsystem requests the DMA cycle if (a) another peripheral wired to this DMA channel has not requested this DMA cycle, (b) there is not a DMA bus acknowledge signal, and (c) the previous request by this peripheral is completed. This assures that another peripheral subsystem wired to this DMA channel and requesting the DMA channel will be operative the next cycle in which thid DMA channel is active.

In a second mode of operation, logic on some peripheral subsystems associated with a particular DMA channel is wired in such a manner that a particular peripheral subsystem wired in that manner requesting the DMA channel and being operative with the DMA channel can remain connected to that DMA channel on successive DMA cycles of that particular channel even through other peripheral subsystems connected to that DMA channel desire access to the channel. In this case, the logic is wired in such a manner that a request for access by the particular peripheral subsystem on the DMA cycles is accepted each time the request is made by that peripheral subsystem. This allows a peripheral subsystem to "hog" that DMA channel for as long as required. A peripheral subsystem operating in a burst mode may have this hogging requirement.

DETAILED DESCRIPTION Fig. 1 shows the system bus timing cycle with the data bus 16 offset from the address bus by 305 ns. The DMA1 time slot is reserved for the cathode ray tube display.

Peripheral subsystems are assigned to the DMA2, DMA3 and DMA4 time slots. The system bus is available to the micrprocessor or CPU cycles.

Fig. 2 is a block diagram of a portion of the overall terminal system comprising a microprocessor subsystem 4, a memory subsystem 1 0, a CRT subsystem 12 inclyding a CRT controller 12-2 and a DMA link and synchronizer 12-4, timing and control logic 2, a DMA priority network 6, option controllers 14a, 1 4b, ., and option data links and synchronizers 22a, 22b, . . A data bus 16, a address bus 18 and a control bus 20 are connected to these subsystems as shown.

The timing and control logic 2 generates the CPUADR- and CPUDAT- bus timing signals which define the DMA and CPU cycle timings of address bus 18 and data bus 16 respectively.

The DMA priority network 6 generates the sequential DMAK10, DMAK20, DMAK30 and DMAK40 timing signals. Timing signal DMAK10 defines the DMA1 address bus 18 and data bus 16 cycle times. Similarly timing signals DMAK20, DMAK30 and DMAK40 define DMA1, DMA3 and DMA4 cycle times respectively.

An option is jumpered serially into one of the timing signal lines to be operative during the DMA cycle. In Fig. 2, option "N" is jumpered serially into timing signal DMAK20 and is operative during the DMA2 address bus 18 and data bus 16 cycle time. Other options (not shown) that would be operative during DMA2 cycle time would be jumpered serially into the continuation of signal line DMAK20, i.e. signal lines DMAK21, DMAK22, etc.

Other options would be jumpered serially into the timing signal chain DMAK30, DMAK31, DMAK32, etc., to be operative at DMA3 time or jumpered serially into the timing signal chain DMAK40, DMAK41, DMAK42, etc., to be operative at DMA4 time.

CRT subsystem 12 is jumpered to timing signal line DMAK10 and is operative at DMA1 time. Since the CRT subsystem requires continuous rewriting, the DMA1 time slot is assigned exclusively to the CRT.

The options 22a, 22b, etc., assigned to be operative during DMA2, DMA3 or DMA4 time are jumpered to signal lines DMAREQ-2, DMAREQ-2 or DMAREQ-3 respectively. One of these lines low indicates that one of the options in that chain is requesting access to its DMA cycle and prevents the others options in that chain from gaining access to the DMA cycle. Fig. 2 shows option "N" 22a jumpered to signal line DMAREQ-2 and option "N + 1" 22b jumpered to signal line DMAREQ-3.

Logic signal DMAREQ + 00, an output of CRT controller 12-2, when high, requests access to the DMA1 cycle by being fed to DMA link and synchronizer 12-4. Logic signal BUSAKI-02 is produced by DMA link 12-4 and acknowledges access to the DMAO cycle when high by feeding CRT controller 12-2.

Each option or device operatively connected to the bus during its DMA cycle either transfers data to or receives data from the memory subsystem over data bus 16 at an address specified by the option or device and sent to memory 10 over address bus 18. Microprocessor subsystem 4 is operative with memory 10 during CPU bus cycles. CPUPH1 and CPUPH2 timing signals, generated by timing and control logic 2, time the microprocessor subsystem 4 to the address bus 18 and data bus 16.

Fig. 3 shows the DMA priority network 6, comprising a free running counter 6-2 and a decoder 6-4 and the DMA linking network 22a.

Counter 6-2 increments by 1 each time the SRBIT3-timing signal goes high. The output signals PR1COD + 01 and PR1COD + 02 indicate binary counts of 00, 01, 10 and 11 on successive positive pulses to the counter 6-2 by timing signal SRBIT3-. Signals PR1COD + 01 and PR1COD + 02 are applied to a decoder 6-4 which produces output signals DMAK10-, DMAK20- and DMAK40on successive SRBIT3- signals. The REFRSH + output signal of counter 6-2 is forced high every 16th rise of the SRBIT3signal. The REFRSH signal is applied to the ENABLE terminal of decoder 6-4 which results in every 4th DMAK10- signal remaining high during the DMA1 time slot. This DMA1 time slot is used to refresh memory 10. The memory refresh operation is not pertinent to present purposes and is therefore not discussed further.

The option "N" controller requests access to memory 10 by forcing signal MYDMAS, an input to a NAND gate 22-2, high. Option "N" is abitrarily wired in series with signal DMAK20-10 which is inverted by inverter 22-24 and again by inverter 22-4 and reaches NAND 22-2 as signal DMAK20-20.

Signal DMAK20-20 when low defines DMA2 cycle time. Signal DMAREQ-02 is jumpered to the DMAREQ-02 signal line and is high when no other option connected in series with signal line DMAK20-10 has requested access to memory 10. The DMAREQ-02 signal is fed to NAND 22-2. The MYDMAG- signal input to NAND 22-2 is high. When the 4 inputs to NAND 22-2 are high, its output, which is fed to the K terminal of a flip-flop 22-6 is low. Timing and control logic 2 generates a DEVSTR- strobe signal which is inverted by inverter 22-22, to give signal DEVSTR +, which is connected to the clock terminal of flip-flop 22-6 which is set on the rise of signal DEVSTR + . Flip-flop 22-6 can be set on any rise of device strobe DEVSTR + when the DMAK20-10 signal is high and no other device in the chain requested memory 10 access.The flip-flop 22-6 output signal MEDMAF + is fed to an OR gate 22-8 and forces the signal DMAK21- high, thereby preventing other options responsive to the DMA2 timing cycle from being operative during this DMA2 cycle. Signal MYDMAF + is inverted by an inverter 22-10 whose output DMAREQ-02 is connected to the DMAREQ-02 bus and to the input of NAND 22-2. This signal when low prevents the other options responsive to the DMA2 timing cycle from being operative by forcing the output of the NAND 22-2 high. (Note that the circuitry described herein is repeated for each option. The DMAREQ-02 signal is connected to the input of NAND 22-2 for each option connected to signal lines DMAK21and DMAREQ-02.) The options that are active during a particular DMA cycle are wired in chain (daisy chain) fashion.Initially, the option wired closest to the DMA priority network 6 has highest priority and the option wired farthest from the DMA priority network 6, that is, at the end of chain, has the lowest priority. The output of OR 8a 22-8 remaining high prevents lower priority options from access to memory 10 during this DMA2 cycle and the output of inverter 22-10 being high prevents higher priority options from access to memory 10 during this DMA2 cycle.

The DMA20-10 signal is inverted by inverter 22-24 which feeds two AND gates 22-12 and 22-14. Signal MYDMAF+ also feeds AND 22-12, and address bus 18 timing signal CPUADR- also feeds this AND 22-12. The CPUADR- signal, when high, gates the valid DMA address signals on address bus 18. When the 3 inputs to AND gate 22-12 are high the output signal MYDMAA goes high, signalling the option "N" controller 14a to send the memory 10 address on address bus 18. Signal MYDMAF- is fed to a NAND gate 22-16 and when low forces the output of NAND 22-16 high. NAND 22-16 feeds AND 22-14. Data bus 16 timing signal CPUDAT- is generated in timing and control logic 2 and is inverted by an inverter 22-20.

The output signal CPUDAT + is also fed to AND 22-14. When the 3 inputs to AND 22-14 are high the output signal MYDMAD goes high, signalling the opt;on "N" controller to either send or receive data over data bus 16.

The signal MYDAMM + is also fed to the J input of a JK flip-flop 22-18. When strobe signal DEVSTR + fed to the clock input goes high, flip-flop 22-18 sets, forcing the output signal MYDMAG- low. Signal MYDMAG- is fed to NAND 22-16 and forces the output high to assure that the MYDMAD signal out put and AND 22-14 remains high until after signal CPUDAT+ goes low.

The MYDMAG + output signal of flip-flop 22-18 forces the J input of flip-flop 22-6 high. The output of NAND 22-2 is also high since the DMAREQ-02 input to NAND 22-2 is low. This forces the K input of flip-flop 22-6 high, resetting the flip-flop on the next DEVSTR + signal. Resetting flip-flop 22-6 allows the DMAREQ-02 request line output of inverter 22-10 to go high. Since the MYDMAF flip-flop 22-6 cannot set again until the MYDMAG flip-flop 22-18 resets, another option in the chain can request the next DMA2 bus cycle.

The present option may have a requirement to access memory 10 on successive DAM2 cycles. In that case the signal DMAREQ-02 input to NAND 22-2 is removed and flip-flop 22-6 can set and access memory 10 during the next DMA2 bus cycle is requested by the option "N" controller 14a, signal MYDMAS.

Output signal MYDMAS goes low when flip-flop 22-6 resets since signal MYD MAF +, the input to AND 22-12, goes low.

This resets flip-flop 22-18 on the next rise of the strobe signal DEVSTR + since the J and K input signals MYDMAA and MYDMAF + are both low.

Fig. 4 shows a timing diagram of the DMA priority operation. The CPUPH1 and CPUPH2 signal timings are to show the relationship of the microprocessor subsystem 4 to the DMA cycles. CPUADR- defines the time DMA address signals are on the address bus 18.

CPUDAT- defines the time DMA data signals are on the data bus 16. DEVSTR + times the option devices to the memory 10 timing. Flipflops set on the rise of the signal.

DMAK20-1O defines the DMA2 bus cycle.

MYDMAF + is set on any rise of DEVSTR + when DMAK20-10 is high. MYDMAG + is set on the rise of DEVSTR + when MYD MAF + is high.

MYDMAA is defined by CPUADR- and MYDMAD is defined by CPUDAT-. Note that MYDMAF + may go high on any rise of DEVSTR + with the exception of those marked A. The dotted portion of MYDMAF + shows the signal going high on the rise of DEVSTR + marked B.

Claims (8)

1. A multi-unit computer priority system, comprising: a common bus to which all units may require access; a revolving priority network which produces a plurality of bus access control signals incyclic sequence; and a plurality of units connected together in chains corresponding to the bus access control signals, each bus access control signal being applied to the first unit in the corresponding chain and passing through each unit not requiring bus access, and any unit requiring bus access achieving such access on receiving a bus access control signal and not passing the signal on down the chain.

2. A system according to Claim 1, including a central processor and a memory coupled to the bus, and wherein the units are peripheral units.

3. A system according to Claim 2, including system bus control and timing logic which assigns bus cycles to the central processor and the peripheral units alternately, the revolving priority network controlling the assignment of the peripheral bus cycles among the peripherals.

4. A system according to any previous claim, wherein the revolving priority network comprises a cyclic counter and a decoder fed from the counter and producing the bus access control signals.

5. A system according to any previous claim, wherein each unit comprises a controller coupled to the bus, and a data link synchronizer coupled to the bus and the controller and to which the bus access control signals are fed, responsive to a bus access request signal from the controller and a bus access control signal to generate an address timing signal and a data timing signal which are fed to the controller to connect it to the bus.

6. A system according to Claim 5, wherein the data link synchronizer comprises bus access request means and bus access acknowledge means, the bus access request means being responsive to the bus access control signals, a bus access request signal, and the bus access acknowledge means to determine whether the unit is being granted bus access, and the bus access acknowledge means being responsive to the bus access request means to terminate access to the bus.

7. A system according to any previous claim, including, for at least one chain, a chain access request line, coupled to all units in the chain, which is energized by any unit in the chain requesting access to the bus and which is coupled to at least one unit in the chain so as to inhibit that unit from requesting access when energized.

8. A multi-unit computer priority system substantially as herein described and illustrated.