JPS5588121A - Direct memory access circulation priority device - Google Patents

Direct memory access circulation priority device

Info

Publication number
JPS5588121A
JPS5588121A JP15752779A JP15752779A JPS5588121A JP S5588121 A JPS5588121 A JP S5588121A JP 15752779 A JP15752779 A JP 15752779A JP 15752779 A JP15752779 A JP 15752779A JP S5588121 A JPS5588121 A JP S5588121A
Authority
JP
Japan
Prior art keywords
memory access
direct memory
priority device
access circulation
circulation priority
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP15752779A
Other languages
English (en)
Japanese (ja)
Other versions
JPS636891B2 (enrdf_load_stackoverflow
Inventor
Inoshita Minoru
Enu Uinfurei Jierarudo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Bull HN Information Systems Italia SpA
Original Assignee
Honeywell Information Systems Italia SpA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Honeywell Information Systems Italia SpA filed Critical Honeywell Information Systems Italia SpA
Publication of JPS5588121A publication Critical patent/JPS5588121A/ja
Publication of JPS636891B2 publication Critical patent/JPS636891B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G06F13/30—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal with priority control

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
JP15752779A 1978-12-26 1979-12-06 Direct memory access circulation priority device Granted JPS5588121A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US97319678A 1978-12-26 1978-12-26

Publications (2)

Publication Number Publication Date
JPS5588121A true JPS5588121A (en) 1980-07-03
JPS636891B2 JPS636891B2 (enrdf_load_stackoverflow) 1988-02-12

Family

ID=25520615

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15752779A Granted JPS5588121A (en) 1978-12-26 1979-12-06 Direct memory access circulation priority device

Country Status (7)

Country Link
JP (1) JPS5588121A (enrdf_load_stackoverflow)
AU (1) AU534761B2 (enrdf_load_stackoverflow)
CA (1) CA1132265A (enrdf_load_stackoverflow)
DE (1) DE2951055A1 (enrdf_load_stackoverflow)
FR (1) FR2445556B1 (enrdf_load_stackoverflow)
GB (1) GB2039105B (enrdf_load_stackoverflow)
YU (1) YU40587B (enrdf_load_stackoverflow)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA1266524A (en) 1983-08-30 1990-03-06 Shinobu Arimoto Image processing system
US4901234A (en) * 1987-03-27 1990-02-13 International Business Machines Corporation Computer system having programmable DMA control
US5241661A (en) * 1987-03-27 1993-08-31 International Business Machines Corporation DMA access arbitration device in which CPU can arbitrate on behalf of attachment having no arbiter
JP2550496B2 (ja) * 1989-03-30 1996-11-06 三菱電機株式会社 Ｄｍａコントローラ
RU2109327C1 (ru) * 1996-08-19 1998-04-20 Тульский государственный университет Многоканальное устройство приоритета

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4831846A (enrdf_load_stackoverflow) * 1971-08-30 1973-04-26

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL154023B (nl) * 1969-02-01 1977-07-15 Philips Nv Prioriteitscircuit.
US3553656A (en) * 1969-06-03 1971-01-05 Gen Electric Selector for the dynamic assignment of priority on a periodic basis
US3961312A (en) * 1974-07-15 1976-06-01 International Business Machines Corporation Cycle interleaving during burst mode operation

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4831846A (enrdf_load_stackoverflow) * 1971-08-30 1973-04-26

Also Published As

Publication number Publication date
AU5300679A (en) 1980-07-03
DE2951055C2 (enrdf_load_stackoverflow) 1990-08-30
YU316779A (en) 1982-06-30
GB2039105B (en) 1983-02-16
GB2039105A (en) 1980-07-30
DE2951055A1 (de) 1980-07-17
FR2445556A1 (fr) 1980-07-25
FR2445556B1 (fr) 1988-03-18
YU40587B (en) 1986-02-28
AU534761B2 (en) 1984-02-16
CA1132265A (en) 1982-09-21
JPS636891B2 (enrdf_load_stackoverflow) 1988-02-12

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