DE2823967C2 - - Google Patents

Info

Publication number
DE2823967C2
DE2823967C2 DE2823967A DE2823967A DE2823967C2 DE 2823967 C2 DE2823967 C2 DE 2823967C2 DE 2823967 A DE2823967 A DE 2823967A DE 2823967 A DE2823967 A DE 2823967A DE 2823967 C2 DE2823967 C2 DE 2823967C2
Authority
DE
Germany
Prior art keywords
type
region
base region
layer
emitter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE2823967A
Other languages
German (de)
English (en)
Other versions
DE2823967A1 (de
Inventor
Kouichi Takahashi
Hidekuni Yokohama Kanagawa Jp Ishida
Toshio Yokosuka Kanagawa Jp Yonezawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Publication of DE2823967A1 publication Critical patent/DE2823967A1/de
Application granted granted Critical
Publication of DE2823967C2 publication Critical patent/DE2823967C2/de
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/167—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table further characterised by the doping material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0804—Emitter regions of bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1004—Base region of bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
    • H01L29/732—Vertical transistors
    • H01L29/7322—Vertical transistors having emitter-base and base-collector junctions leaving at the same surface of the body, e.g. planar transistor
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/965—Shaped junction formation

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Bipolar Transistors (AREA)
DE19782823967 1977-06-09 1978-06-01 Npn-transistor Granted DE2823967A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6730777A JPS543479A (en) 1977-06-09 1977-06-09 Semiconductor device and its manufacture

Publications (2)

Publication Number Publication Date
DE2823967A1 DE2823967A1 (de) 1978-12-14
DE2823967C2 true DE2823967C2 (US06534493-20030318-C00288.png) 1988-12-08

Family

ID=13341216

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19782823967 Granted DE2823967A1 (de) 1977-06-09 1978-06-01 Npn-transistor

Country Status (3)

Country Link
US (4) US4226650A (US06534493-20030318-C00288.png)
JP (1) JPS543479A (US06534493-20030318-C00288.png)
DE (1) DE2823967A1 (US06534493-20030318-C00288.png)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4035842A1 (de) * 1990-11-10 1992-05-14 Telefunken Electronic Gmbh Verfahren zur rekristallisierung voramorphisierter halbleiteroberflaechenzonen

Families Citing this family (23)

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JPS543479A (en) * 1977-06-09 1979-01-11 Toshiba Corp Semiconductor device and its manufacture
GB2056168A (en) * 1979-08-01 1981-03-11 Gen Instrument Corp Method of fabricating P-N junction with high breakdown voltage
US4804634A (en) * 1981-04-24 1989-02-14 National Semiconductor Corporation Integrated circuit lateral transistor structure
US4420344A (en) * 1981-10-15 1983-12-13 Texas Instruments Incorporated CMOS Source/drain implant process without compensation of polysilicon doping
US4431460A (en) * 1982-03-08 1984-02-14 International Business Machines Corporation Method of producing shallow, narrow base bipolar transistor structures via dual implantations of selected polycrystalline layer
JPS5933860A (ja) * 1982-08-19 1984-02-23 Toshiba Corp 半導体装置およびその製造方法
US4621411A (en) * 1984-09-28 1986-11-11 Texas Instruments Incorporated Laser-enhanced drive in of source and drain diffusions
IT1214808B (it) * 1984-12-20 1990-01-18 Ates Componenti Elettron Tico e semiconduttore processo per la formazione di uno strato sepolto e di una regione di collettore in un dispositivo monoli
EP0213919B1 (en) * 1985-08-26 1991-06-26 Kabushiki Kaisha Toshiba Semiconductor devices and method of manufacturing same by ion implantation
IT1188309B (it) * 1986-01-24 1988-01-07 Sgs Microelettrica Spa Procedimento per la fabbricazione di dispositivi elettronici integrati,in particolare transistori mos a canale p ad alta tensione
GB2188478B (en) * 1986-03-26 1989-11-22 Stc Plc Forming doped wells in sillicon subtstrates
US4889492A (en) * 1986-05-07 1989-12-26 Motorola, Inc. High capacitance trench capacitor and well extension process
JPH0828423B2 (ja) * 1988-10-14 1996-03-21 日本電気株式会社 半導体記憶装置
US5023891A (en) 1989-07-25 1991-06-11 Sf2 Corporation Method and circuit for decoding a Manchester code signal
US5185276A (en) * 1990-01-31 1993-02-09 International Business Machines Corporation Method for improving low temperature current gain of bipolar transistors
US5091321A (en) * 1991-07-22 1992-02-25 Allegro Microsystems, Inc. Method for making an NPN transistor with controlled base width compatible with making a Bi-MOS integrated circuit
US5520752A (en) * 1994-06-20 1996-05-28 The United States Of America As Represented By The Secretary Of The Army Composite solders
US5882961A (en) * 1995-09-11 1999-03-16 Motorola, Inc. Method of manufacturing semiconductor device with reduced charge trapping
US6750482B2 (en) 2002-04-30 2004-06-15 Rf Micro Devices, Inc. Highly conductive semiconductor layer having two or more impurities
US20040121524A1 (en) * 2002-12-20 2004-06-24 Micron Technology, Inc. Apparatus and method for controlling diffusion
US7297617B2 (en) * 2003-04-22 2007-11-20 Micron Technology, Inc. Method for controlling diffusion in semiconductor regions
US8110469B2 (en) 2005-08-30 2012-02-07 Micron Technology, Inc. Graded dielectric layers
US9634098B2 (en) 2013-06-11 2017-04-25 SunEdison Semiconductor Ltd. (UEN201334164H) Oxygen precipitation in heavily doped silicon wafers sliced from ingots grown by the Czochralski method

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Publication number Priority date Publication date Assignee Title
US3707410A (en) * 1965-07-30 1972-12-26 Hitachi Ltd Method of manufacturing semiconductor devices
GB1145121A (en) * 1965-07-30 1969-03-12 Associated Semiconductor Mft Improvements in and relating to transistors
GB1099049A (en) * 1965-12-28 1968-01-10 Telefunken Patent A method of manufacturing transistors
US3493443A (en) * 1967-05-25 1970-02-03 Bell Telephone Labor Inc Hyperabruptp-n junctions in semiconductors by successive double diffusion of impurities
DE1614827C2 (de) * 1967-06-22 1979-06-21 Telefunken Patentverwertungsgesellschaft Mbh, 7900 Ulm Verfahren zum Herstellen eines Transistors
FR1569872A (US06534493-20030318-C00288.png) * 1968-04-10 1969-06-06
NL140657B (nl) * 1968-06-21 1973-12-17 Philips Nv Werkwijze voor het vervaardigen van een halfgeleiderinrichting door een diffusiebehandeling en halfgeleiderinrichting, vervaardigd volgens deze werkwijze.
JPS4826179B1 (US06534493-20030318-C00288.png) * 1968-09-30 1973-08-07
US3717507A (en) * 1969-06-19 1973-02-20 Shibaura Electric Co Ltd Method of manufacturing semiconductor devices utilizing ion-implantation and arsenic diffusion
US3704178A (en) * 1969-11-05 1972-11-28 Bryan H Hill Process for forming a p-n junction in a semiconductor material
US3608189A (en) * 1970-01-07 1971-09-28 Gen Electric Method of making complementary field-effect transistors by single step diffusion
US3748198A (en) * 1970-01-22 1973-07-24 Ibm Simultaneous double diffusion into a semiconductor substrate
US3812519A (en) * 1970-02-07 1974-05-21 Tokyo Shibaura Electric Co Silicon double doped with p and as or b and as
US3834953A (en) * 1970-02-07 1974-09-10 Tokyo Shibaura Electric Co Semiconductor devices containing as impurities as and p or b and the method of manufacturing the same
US3730787A (en) * 1970-08-26 1973-05-01 Bell Telephone Labor Inc Method of fabricating semiconductor integrated circuits using deposited doped oxides as a source of dopant impurities
DE2211709C3 (de) * 1971-03-12 1979-07-05 Hitachi, Ltd., Tokio Verfahren zum Dotieren von Halbleitermaterial
US3798084A (en) * 1972-08-11 1974-03-19 Ibm Simultaneous diffusion processing
US3915767A (en) * 1973-02-05 1975-10-28 Honeywell Inc Rapidly responsive transistor with narrowed base
US4006046A (en) * 1975-04-21 1977-02-01 Trw Inc. Method for compensating for emitter-push effect in the fabrication of transistors
JPS543479A (en) * 1977-06-09 1979-01-11 Toshiba Corp Semiconductor device and its manufacture

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4035842A1 (de) * 1990-11-10 1992-05-14 Telefunken Electronic Gmbh Verfahren zur rekristallisierung voramorphisierter halbleiteroberflaechenzonen

Also Published As

Publication number Publication date
US4667218A (en) 1987-05-19
US4226650A (en) 1980-10-07
US4263067A (en) 1981-04-21
JPS543479A (en) 1979-01-11
DE2823967A1 (de) 1978-12-14
US4778772A (en) 1988-10-18

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Legal Events

Date Code Title Description
OAP Request for examination filed
OD Request for examination
8127 New person/name/address of the applicant

Owner name: KABUSHIKI KAISHA TOSHIBA, KAWASAKI, KANAGAWA, JP

D2 Grant after examination
8364 No opposition during term of opposition