DE2622790A1 - Verfahren und anordnung zur kantenaetzung fuer die herstellung schmaler oeffnungen zu materialoberflaechen - Google Patents

Verfahren und anordnung zur kantenaetzung fuer die herstellung schmaler oeffnungen zu materialoberflaechen

Info

Publication number
DE2622790A1
DE2622790A1 DE19762622790 DE2622790A DE2622790A1 DE 2622790 A1 DE2622790 A1 DE 2622790A1 DE 19762622790 DE19762622790 DE 19762622790 DE 2622790 A DE2622790 A DE 2622790A DE 2622790 A1 DE2622790 A1 DE 2622790A1
Authority
DE
Germany
Prior art keywords
layer
narrow opening
lateral edge
etching
narrow
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
DE19762622790
Other languages
German (de)
English (en)
Inventor
Harold Hazlett Hosack
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fairchild Semiconductor Corp
Original Assignee
Fairchild Camera and Instrument Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US05/619,735 external-priority patent/US4063992A/en
Application filed by Fairchild Camera and Instrument Corp filed Critical Fairchild Camera and Instrument Corp
Publication of DE2622790A1 publication Critical patent/DE2622790A1/de
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D44/00—Charge transfer devices
    • H10D44/40—Charge-coupled devices [CCD]
    • H10D44/45—Charge-coupled devices [CCD] having field effect produced by insulated gate electrodes 
    • H10D44/462—Buried-channel CCD
    • H10D44/466—Three-phase CCD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D44/00—Charge transfer devices
    • H10D44/40—Charge-coupled devices [CCD]
    • H10D44/45—Charge-coupled devices [CCD] having field effect produced by insulated gate electrodes 
    • H10D44/462—Buried-channel CCD
    • H10D44/464—Two-phase CCD
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0198—Integrating together multiple components covered by H10D44/00, e.g. integrating charge coupled devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Solid State Image Pick-Up Elements (AREA)
  • Element Separation (AREA)
  • Weting (AREA)
  • Drying Of Semiconductors (AREA)
DE19762622790 1975-05-27 1976-05-21 Verfahren und anordnung zur kantenaetzung fuer die herstellung schmaler oeffnungen zu materialoberflaechen Withdrawn DE2622790A1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US58138975A 1975-05-27 1975-05-27
US05/619,735 US4063992A (en) 1975-05-27 1975-10-06 Edge etch method for producing narrow openings to the surface of materials

Publications (1)

Publication Number Publication Date
DE2622790A1 true DE2622790A1 (de) 1976-12-09

Family

ID=27078310

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19762622790 Withdrawn DE2622790A1 (de) 1975-05-27 1976-05-21 Verfahren und anordnung zur kantenaetzung fuer die herstellung schmaler oeffnungen zu materialoberflaechen

Country Status (6)

Country Link
JP (1) JPS51145274A (enExample)
CA (1) CA1076934A (enExample)
DE (1) DE2622790A1 (enExample)
FR (1) FR2312856A1 (enExample)
GB (1) GB1543845A (enExample)
NL (1) NL7605549A (enExample)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3128629A1 (de) * 1980-07-21 1982-06-09 Data General Corp., 01581 Westboro, Mass. Rueckaetzverfahren fuer integrierte schaltkreise
DE4102583A1 (de) * 1990-01-29 1991-08-01 Mitsubishi Electric Corp Ladungstransfereinrichtung

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS544570A (en) * 1977-06-13 1979-01-13 Nec Corp Production of semiconductor devices
JPS5533064A (en) * 1978-08-29 1980-03-08 Chiyou Lsi Gijutsu Kenkyu Kumiai Method of manufacturing semiconductor device
FR2454698A1 (fr) * 1979-04-20 1980-11-14 Radiotechnique Compelec Procede de realisation de circuits integres a l'aide d'un masque multicouche et dispositifs obtenus par ce procede
DE2939456A1 (de) * 1979-09-28 1981-04-16 Siemens AG, 1000 Berlin und 8000 München Verfahren zur herstellung von integrierten halbleiterschaltungen, insbesondere ccd-schaltungen, mit selbstjustierten, nichtueberlappenden poly-silizium-elektroden
DE2939488A1 (de) * 1979-09-28 1981-04-16 Siemens AG, 1000 Berlin und 8000 München Verfahren zur herstellung von integrierten halbleiterschaltungen, insbesondere ccd-schaltungen, mit selbstjustierten, nicht ueberlappenden poly-silizium-elektroden
US4317690A (en) 1980-06-18 1982-03-02 Signetics Corporation Self-aligned double polysilicon MOS fabrication
JPS581878A (ja) * 1981-06-26 1983-01-07 Fujitsu Ltd 磁気バブルメモリ素子の製造方法
RU2112300C1 (ru) * 1995-03-10 1998-05-27 Институт физики полупроводников СО РАН Способ изготовления защитной маски для нанолитографии
US6965165B2 (en) 1998-12-21 2005-11-15 Mou-Shiung Lin Top layers of metal for high performance IC's

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL7005296A (enExample) * 1969-04-15 1970-10-19
JPS4874178A (enExample) * 1971-12-29 1973-10-05
FR2305022A1 (fr) * 1975-03-21 1976-10-15 Western Electric Co Procede de fabrication de transistors

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3128629A1 (de) * 1980-07-21 1982-06-09 Data General Corp., 01581 Westboro, Mass. Rueckaetzverfahren fuer integrierte schaltkreise
DE4102583A1 (de) * 1990-01-29 1991-08-01 Mitsubishi Electric Corp Ladungstransfereinrichtung

Also Published As

Publication number Publication date
NL7605549A (nl) 1976-11-30
GB1543845A (en) 1979-04-11
AU1437576A (en) 1977-12-01
FR2312856A1 (fr) 1976-12-24
FR2312856B1 (enExample) 1982-11-05
JPS5711505B2 (enExample) 1982-03-04
CA1076934A (en) 1980-05-06
JPS51145274A (en) 1976-12-14

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Legal Events

Date Code Title Description
8110 Request for examination paragraph 44
8139 Disposal/non-payment of the annual fee