CA1076934A - Edge etch method and structure for producing narrow openings to the surface of materials - Google Patents

Abstract

ABSTRACT

An improved method and structure for producing narrow openings to the surface of a first material processing a first set of etch characteristics is disclosed. The method includes the step of forming on a portion of the surface of the first material an etchable mask having a first narrow-opening-forming lateral edge disposed along a selected edge of the to-be-formed narrow opening. A protective layer of a second material possessing a second set of etch characteristics is next formed on the exposed surface of the first material, the protective-layer having a second narrow-opening-forming lateral edge juxtaposed the first narrow-opening-forming lateral edge.
The first narrow-opening-forming lateral edge on the mask is then etched to expose unprotected areas of the first material-thereby producing the narrow opening to the surface of the first material. The method and structure of the invention is particularly well suited for producing fine geometry patterns in solid state device structures.

Description

107693~

BACKG~OIlND ~F THE INVFNTI~N

2 Field of the Invention:

3 This invention relates generally to a method and structure for producing narrow openings to the surfaces of materials, and, more particularly, relates to a method and structure 6 which is well suited for manufacturin~ inte~rated-circuit 7 semiconductor devices having fine geometry patterns.
8 Description of the Prior Art:
9 Techniques for producing narrow openings to the sur~ace of a material are known. ~ne of the most ~opular techniques, 11 which is widely used in the semiconductor industry, involves 12 forming a layer of photoresist on the sur~ace of a material, 13 selectively exposing portions of the ~hotoresist to ultraviolet 14 light and developing the exposed photoresist. The widths o~
openings produced using this technique are limited by dif-16 fraction and reflection effects at the wavelengths of the l7 radiation used to expose the photoresist. Narrower openings l8 can be produced by analogous methods employing different Ig photoresist materials and radiation o~ shorter wavelength such . 20 as an electron beam or X-rays. A thorough discussion of the 21 limitations of conventional photolitho~raphy can be found in 22 the ~July 1975 issue of the IEEE Transactions on Electron 23 Devices.
24 Another techni~ue used to produce a narrow emitter opening in a semiconductor device is disclosed in a paper titled "A
26 New Sub-Micron Emitter Formation with Re~uced ~ase Resistance 27 for IJltra High-Speed Devices" by H. Kamioka et al, presented 28 in nece~ber 1974 to the International Electron Devices Meeting 29 held in Washington, D. C. and puhlished starting on page 279 in the technical digest of that meeting. Kamioka et al's ..... ~ _ _ Ç_ ¦ F-1230/l 1 1~76934 ¦ technique forms a three-micron-wide layered sandwich of silicon 21 nitride, silicon dioxide and silicon nitride centered over the 31 desired location of the emitter opening on the surface of a 41 silicon substrate. The sandwiched layer of silicon dioxide 51 is then laterally etched inward from both sides to form 61 with the two nitride layers a structure with "I-heam" cross-1 sectional configuration. The vertical rib of remaining silicon 8¦ dioxide protectively masks an underlying ribbon (stated to be 91 0 5 micron wide) of silicon nitride while the exposed portions 10¦ of silicon nitride are etched away from both sides. The 11¦ overlying masking silicon dioxide rib is subsequently removed 12¦ and a layer of silicon dioxide is formed on the exposed surface 13 ¦ of the silicon substrate. The remaining ribbon of silicon 14 ¦ nitride, which defines both the width and location of the 15 ¦ narrow emitter openin~, is then removed, thereby exposing a 16 ¦ portion of the silicon substrate surface.
17 ¦ The selective lateral etching of a small-area-bounding 18 ¦ lateral edge on an adjacent overlying layer of one material to 19¦ expose a larger area of the underlying material is shown in 20 ¦. U. S. Patent No. 3,783,047 issued to M. M. Paffen et al on 21 ¦ January l, 1974 and titled "Method of Manufacturing a Semi-22; ¦ conductor Device and Semiconductor ~evice Manufactured by 23 ¦ Using Such a Method." The method taught ~y Paffen et al is 24 ¦ used to produce a semiconductor device having a small zone with 25 ¦ one selected set of electrical properties and a larger zone 26 ¦ with another set of electrical properties.
27 ¦ The use of a selective lateral etch is described by -28 ~ C. N. B~glund et al in a paper entitled "IJndercut Isolation --29 ¦ A Technique for Closely Spaced and ~Self-Ali~ned Metalization 30 ¦ Patterns for MnS Integrated Circuits." This paper was published 10769;~

1 in September, 1973 beginning on page 1255 of Vol. 120, No. 9 of 2 the Journal of the Electrochemical Society. C.~. Berglund et al 3 take advantage of the shadowing effect of an undercut area etched in a two-layer-insulator sandwich. Because of the masking effect of an undercut edge a thin metal film evaporated at an 6 appropriate angle to the edge will be discontinuous at the 7 undercut edges, resulting in electrically isolated metalization 8 patterns at different vertical levels with negligible lateral 9 spacing between them. Berglund et al illustrate an application , for this technique by describin~ the des;gn of a two-phase CCD
Il (Charge-Coupled Device).
12 Although electron-beam and X-ray lithography techniques can 13 be used to produce narrow openings which make possible smaller l4 semiconductor elements and higher chip density than previously obtained using less advanced methods, these techniques have 16 many disadvantages. Not only is the equipment required to prac-l7 tice the electron-beam technique presently very expensive, but 18 the technique also presently requires prolonged photoresist l9 exposure times which are unsuitable for mass production. Opti-mized equipment required to practice X-ray lithography on a .... , " , .
21 production scale is not currently available. Moreover, in 22 addition to the well-known hazar~s and fail-safe precautionary 23 measures associated with the use of X-rays, the technique require 24 a high precision mask often made of heavy metal, such as gold, possessing geometries as fine as those to be produced on the sur-26 face of the material. Such masks are generally produced with 27 electron-beam techniques and are both expensive and difficult .28 to pr~odu~e.
29 The width of narrow openings producible with the double-30 ¦ sided etch method of Kamioka et al is limited by the fact that ~;, - _ ~ F-lZ30/1 1~7693~

1 the silicon dioxide rib must be sufficiently wide to support 2 the overllangillg layer of silicon nitride. Additionally, 3 although the lateral etch rate of silicon dioxide is in theory controllable to render the depth of undercut a function of etch time, as the depth of undercut is increased to produce an ever-narrower silicon dioxide rib, the difficulty in 7 controlling etch rate, etch uniformity and hence the width of the to-be-formed opening increases. Further, as the etch 9 process occurs simultaneously from two sides, the uncertainty in the width of the to-be-formed opening increases due to the Il combined uncertainty in the locations of the converging edges 12 at any given time.
13 ~

~076934 The present invention, in contrast to Kamioka et al's technique, achieves narrower openings by reducing rather than increasing the lateral etch time and by etching only one, rather than two, lateral edges of a mask-ing material to produce each narrow opening. Therefore, the present invention is not structurally limited as is the Kamioka et al technique in the narrow-ness of openings it can be used to produce. Moreover, since a shorter etch time is required for a narrower to-be-formed opening, the non-uniformities in the width of the to-be-formed opening due to local variations in the etch rate tend to be reduced. In addition, since a narrow opening is pro-duced at each edge of a masking material by the present invention, the density of narrow openings is increased over the Kamioka et al technique.
Thus, the process of this invention overcomes many of the difficulties associated with prior-art methods used to produce narrow openings to ~he surface of a material. It does so by providing a novel method that is particularly attractive to the semiconductor industry in that it may be practiced with only materials and processes that are commonly used and well understood in that industry. This is in direct contrast to the more esoteric prior-art methods of electron-beam and X-ray lithography which have been used to produce similar narrow openings to the surface of a material.
In accordance with the present invention, there is provided a planar process for producing a charge-coupled device of the type having a single level of electrodes separated from one another by narrow gaps compris-ing the steps of: forming an electrically insulating layer on a substantial-ly planar surface of a semiconductor substrate; forming an electrically conductive layer on the upper surface of said electrically insulating layer;
forming a plurality of narrow interelectrode gaps in said electrically con-ductive layer, each interelectrode gap being formed by a process comprising the steps of; forming on a portion of said electrically conductive layer an etchable mask having a first narrow-opening-forming lateral edge disposed along a selected edge of the to-be-formed interelectrode gap; forming a protective layer of a material possessing a set of etch characteristics different from etch characteristics of said electrically conductive layer 1~76934 on the adjacent exposed surface of said electrically conductive layer, said protective layer being formed at a thickness substantially less than the thickness of said etchable mask and with a second narrow-opening-forming lateral edge contiguous to and juxtaposed said first narrow-opening-forming lateral edge; etching said first narrow-opening-forming lateral edge on said mask to expose an unprotected portion of said electrically conductive layer to produce a narrow opening to the surface of said electrically conductive layer; and etching said electrically conductive layer through said narrow opening and down to said electrically insulating layer to thereby form one of said narrow interelectrode gaps.
Further, a structure for use in producing a narrow opening to the surface of a first material possessing a first set of etch characteristics is described which comprises an etchable mask formed on a portion of the surface of the first material, the mask having a first narrow-opening-form-ing lateral edge disposed along a selected edge of the to-be-formed narrow opening and a protective layer of a second material possessing a second set of etch characteristics formed on the exposed portion of the surface of the first material, the protective layer having a second narrow-opening-forming lateral edge juxtaposed the first narrow-opening-forming lateral edge, whereby the first narrow-opening-forming lateral edge is etchable to expose unprotected areas of the first material thereby producing the narrow opening to the surface of the first material.

.~

- , . ~-1230/1 1(17693~

BRIEF DESCRIPTION OF Til~ Dr~INGS
2 The many oojects and aavanta~es of the present invention 3 will become apparent to those skilled in the art when the

4 following description of the best mode contemplated for practicin~ the invention is read in conjunction with the 6 accompanying drawings, wherein like reference characters refer 7 to the same or similar elements, and in which:
8 FIGS. 1 through 15 are stylized partial cross-sectional 9 views of starting, inter]nediate and final structures employed in the practice of the invention;
11 FIG 16 is a stylized partial cross-sectional view of a 12 three-phase charge-coupled device;
13 FIG 17 is a stylized partial cross-sectional view of a 14 two-phase buried channel, implanted barrier charge-coupled device;
16 FIG 18 is a stylized partial cross-sectional view of a 17 two-phase, buried channel, implanted barrier charge-coupled 18 device utilizing two overlapping levels of electrodes;
19 FIGS l9a througll l9j are stylized partial cross-sectional 20 views of structures which illustrate the edge etch process of 21 this invention used in the fabrication of a single level poly-22 silicon electrode, buried channel, implanted barrier charge-23 coupled device in which the individual electrodes are separated 24 by narrow gaps;
FIGS 20a through 20p are stylized partial cross-sectional 26 views of structures used in the fabrication of a two-phased 27 buried channel, implanted barrier charge-coupled device having 28 two o~erLapping levels of electrodes in whicll the narrow ~aps 29 between individual electrodes on both levels are produced 30 Wit}l the edge etch technique of the invention;

r: ~ ~

I . ~ 3()/l 1 1(~7693f~

¦ FIGS 21a through 21j are stylized partial cross sectional 2I views of structures used to produce narrow lateral oxidized .
31 isolation regions in a polysilicon layer using the edge etch I technique of the invention;
5I FIGS. 22a through 22g are stylized partial cross-sectional 61 views of structures used to subdivide a thin silicon epitaxial ~
71 layer into electrically isolated pockets by a grid of oxidized 8 ¦ isolation regions of epitaxial silicon ~aterial which extend 9 ¦ through the epitaxial layer to a laterally extending isolation , lO ¦ pn junction using the edge etch technique of the invention; and ¦ FIGS 23a through 23h are stylized partial cross-sectional 12 ¦ views of structures used to subdivide with narrow gaps a 13 metalization layer using the edge etch technique of the 14 invention.
I~ ~1///

22 l 24~

28 . _ 1~ 1)/1 1~7693~

DF,TAILED DESCRIPTI(`)N
2 The invention provides a generalized method and structure .
3 for providing a narrow opening through an overlyin~ material 4 or materials to the surface of a first material. An under-standing of this method and structure will be achieved by 6 reference first to FIG 1 which is a partial cross-sectional view of such a first material 10. The first material 10 8 possesses a first set of etch characteristics and a substantially 9 planar surface 12. In order to form a narrow opening to the surface 12 of the first material 10 at a`selecte~ location 14, ll an etchable mask 16 is formed in a selected pattern on a 12 portion of the surface 12 of the first material 10 as shown 13 in FIG 2. The etchable mask 16 possesses a first narrow-14 opening-forming lateral edge 18. The lateral edge 18 is shown throughout the several figures disposed substantially per-16 pendicular to the surface 12 of the first material 10. However, 17 it is to be understood that throughout this application 18 whenever reference is made to a "lateral edge" such an edge l9 may be disposed perpendicularly or at an angle to the surface 12 and further that such a "lateral edge" can be straight, or .... ,.. ...
~l concave, or convex, or some compound comhination thereof.
22 Next, a protective layer of a second material 20 possessing a 23 second set of etcn characteristics is formed on the exposed 24 surface 12 of the first material 10. The protective lay0r of 2S second material 20 possesses a second narrow-opening-forming 26 lateral edge 22 juxtaposed the .first narrow-opening-forming 27 lateral edge 18 as is shown in FIG 3. Lastly, the first ..28 narrow-Qpening-forming lateral edge 18 on the etchable mask 16 29 is etched a selected distance away from the second narrow-30 ¦ opening-forming lateral edge 22 to form a resultant narrow-.~ _ 1~7693~

1 opening-forming lateral edge 24 thereby ~roducing the desired 2 narrow opening to the surface 12 of the first material 10 at 3 the selected location 14 as shown in FIG 4.
4 In the most elementary configuration of this invention the etchable mask 16 comprises a single region-defining layer 6 26 of a third material possessing a third set of etch character-7 istics. When the first narrow-opening-forming lateral edge 18 8 is etched back to form the resultant lateral edge 24, the upper 9 surface of the etchable mask 16 is simultaneously etched away.
This is acceptable so long as after the desired narrow opening Il has been formed at the selected location 14 there remains a 12 sufficient amount of the etchable mask 16 to protect that 13 portion of the surface 12 which is to remain unexposed.
14 To obtain more control of the lateral etching of the first narrow-opening-forming lateral edge 18 and to reduce the 16 required thickness of the region-defining layer 26 of third 17 material, a layer of fourth material 28 possessing a fourth 18 set of etch characteristics can be provided. The layer of 19 fourth material 28 is adherently disposed in overlying regi-stration with the third material 26 on its upper surface as 21 shown in FIG 5. The layer of fourth material 28 possesses 22 a lateral edge 30 which is disposed above and along the first 23 narrow-opening-forming lateral edge 18. The particular 24 arrangement of materials shown in FIG 5 can be provided by several techniques well known to those versed in semiconductor 26 manufacturing technology. For example, successive depositions 27 can be made of the third and fourth materials with a shadow 28 mask pr~tectively covering that portion of the surface 12 of 29 the first material 10 on which a layered region is not desired.
Another method of forming the structure shown in FIG 5 is by _ , ~ _ I , ~ 0/1 .

1 10769~

¦ deposition of uniform layers of third and fourth materials on 21 the surface 12 of the first material 10 followed by photolitho- .
3 graphic definition and etching steps common to the semiconductor 4 industry. As is shown in FIG. 6, the protective layer of second material 20 can then be formed on the exposed portions of the 6 surface 12 and the first narrow-opening-forming lateral edge 7 18 selectively etched away to form the resultant lateral edge 8 24 producing the desired narrow opening to the surface 12 of 9 the first material 10 at the selected location 14 as shown in FIG 7. Alternatively, the lateral edge 30 on the layer of 11 fourth material 28 as shown in FIG 5, can be selectively etched 12 to form a third narrow-opening-forming lateral edge 36 as is 13 shown in FIGS 8 and 9. It will be understood that the selective 14 etching of the lateral edge 30 on layer of fourth material 28 can occur prior or subsequent to the formation of the protective 16 layer 20 on the exposed surface 12 of the first material 10.
17 In either case, the structure shown in FIG. 9 results and the 18 exposed portions of the layer of third material 26 are then l9 etched away forming the desired narrow opening to the surface 12 of the first material 10 at the selected location 14 as is ~1 shown clearlv in FIG. 10.
22 Greater control of the lateral etching of the lateral 23 ¦ edge 30 on the layer of fourth material 28 to form the third 24 ¦ narrow-opening-forming lateral edge 36 can be achieved through ~5 the use of a three layer etchable mask 16. Such a three l,~Yer 26 mask is shown in FIG 11 wherein the third layer comprises a 27 layer of fifth material 32 possessing a fifth set of etch 28 charact~ristics adherently disposed in overlying registration 29 with the layer of fourth material 28 on its upper surface.
The layer of fifth material 32 possesses a lateral edge 34 _ 1~7693~

which is disposed above and along the lateral edge 30 on the layer of fourth material 28. The three layer etchable mask 16 shown in Figure 11 can be provided by techniques analogous to those used to form the two layer mask shown in Figure 5 and de-scribed above. After the structure in Figure 11 has been formed, the lateral edge 30 on the layer 28 of fourth material is etched to form the third narrow-opening-forming lateral edge 36 as is shown in Figure 12. The layer of fifth material 32 protectively ::
covers the upper surface of the layer of fourth material 28 during at least a portion of the etch. Next, the protective layer of second material 20 is formed on the exposed surface 12 of the first material 10 as is shown in Figure 13. Lastly, the portions of the layer of third material 26 exposed between the second and third narrow-opening-forming lateral edges, 22 and 36 respectively, are etched away forming the desired narrow-opening to the surface 12 of the first material 10 at the selected location 14 as is clearly shown in Figure 14. Alter-natively, as is shown in Figure 15, the protective layer of second material 20 can be formed on the exposed surface 12 of the first material 10 before the edge 30 on the layer of fourth material 28 is etched.
It is to be understood that when the method of the invention is practiced with a single layer etchable mask 16 the structures shown in the series of Figures 1, 2, 3, and 4 are formed sequentially. Similarly, when a two layer etchable mask 16 is used to practice the method of the invention, the structures shown in the series of Figures 1, 5, 6, and 7, or in the series of Figures 1, 5, 8, 9, and 10, or in the series of -Figures 1, 5, 6, 9, and 10 are formed sequentially. In like manner, when a three layer etchable mask 16 is employed, the structures shown in the series ~ U/l 1~7693~

1 of FIG~ 1, 11, 12, 13 and 14 or in the series of FIGS 1, 11, 2 15, 13 and 14 are formed sequentially. Additionally, it is 3 to be further understood that in a selected etch step it is possible that the physical or chemical processes selected to etch an exposed portion of one selected material to form a 6 desired configuration of materials can also etch exposed portions 71 of other materials. However, the various thicknesses and etch 8~ characteristics of all materials must be such that when the 9 ¦ narrow opening to the surface 12 of the irst material lû at ' 10¦ the selected location 14 is cleared, there remains some part ll¦ of the protective layer of second material 20 and some part 12¦ of the region defining layer of third material 26 in those 13 ¦ areas not desired to be openings.
l4 ¦ FIGS 1 through 15 are intentionally shown in stylized 15 ¦ form without cross-sectional cross-hatching sug~estive of specifi 16 ¦ materials. These figures are so rendered in an effort to em-17 ¦ phasize the broad scope of the process and structure of the 18 ¦ invention. Specific examples of portions of useful articles 19 I of manufacture which embody and serve to further illustrate 20 ¦ the process and structure of the invention using specific 21 ¦ selected materials are provided hereinbelow. For detailed 22 I information concerning individual process steps which are 23 recited in the examples below the reader is directed to 24 numerous patents, papers and books in the semiconductor arts of which the text by A. S. Grove entitled: PHYSIC~S ANn TF,CHNO-26 LOGY OF SEMICONDUCTOR DEVICES,-published by John Wiley and Sons, 27 Inc., N. Y., N. Y. 1967; and the text by L. I. Maissel and 28 R. Gl-ang~entitled: HANDBOOK OF THIN FILM TECHNOLOGY, published 29 by McGraw-Hill ~ook Co., N. Y., N. Y. 1970, are illustrative.
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1(:~7693~

1 CHARGE C~UPLFD DF.VICES
2 W S. ~oyle and G. E. Smith described the basic concept 3 of charge coupled semiconductor devices in an article published 41 in the April 19, 1970 Bell System Technical Journal, page 587, 51 entitled "Charge-Coupled Semiconductor nevices". Such devices -61 consist of a metal-insulator-semiconductor structure in which 71 minority carriers are stored in "spatially defined depletion 81 regions", also called "potential wells", at the surface of the gI semiconductor material. Such devices are useful not only as 10¦ shift regis~ers and delay lines but are also useful as imaging 11¦ devices possessing dynamic range and/or sensitivity character-12 ¦ istics that depend upon the physical features of the metal-13 ¦ insulator-semiconductor structure.
14 ¦ A method of producing such spatially defined deplètion 15 ¦ regions with appropriate properties was first described by 16 ¦ Amelio et al, in an article entitled "Fxperimental Verification 17 ¦ of the Charge Coupled Device Concept", published in the April 18 ¦ l9, 1970 Bell System Technical Journal, page 593.
19 1 A CCD structure as described therein is formed with a 20 ¦ series of Metal-Oxide-Semiconductor (Mn~S) capacitors separated 21 ¦ by non-conducting gaps as shown in FI~ 16. This structure i 22 ¦ comprises a monocyrstalline silicon semiconductor substrate 23 ¦ 50 of p type conductivity. An insulating layer of silicon 24 ¦ dioxide 52 is formed on the upper surface of the substrate 50 and a plurality of aluminum electrodes 54 are disposed longi-26 tudinally on the layer 52 in spaced apart relationship a selected 27 gap distance 56 fro~ one another. These first ccn structures 28 were of three-phase design. In such a des~n the potential 29 wells are defined by the lateral extremities of the electrodes 54. C r~e is transferred aIoAg the device structure by ¦ ~ F-1230/1 l 1~7693~
I . .
1¦ providing a different selected clock voltage signal 01~ ~2 21 and 03 to each of three sets of electrodes formed by the elec-3 ¦ trical interconnection of every third electrode as shown. In 4 I these first devices the reported gap dimension 56 was 3 microns.
Subsequent investigations showed that poor transfer efficiency 6 and unstable performance in this type of device could be 71 attributed to the uncontrolled surface potential in the gap 81 region between the conducting électrodes.
9¦ Another CCD design is the two-phase, buried channel, , 10¦ implanted barrier structure shown in FIG 17. In this design 11 ¦ a buried channel region 58 of n type conductivity is disposed 12 I in the surface of the substrate 50. Barrier regions 60 of n-13 ¦ type conductivity are periodically disposed in the surface of l4 ¦ the substrate to define the lateral extremities o~ the 15 ¦ potential wells. These barrier regions also function to effect 16 ¦ the unidirectional flow of signal charge. The buried channel 17 ¦ region 58 and barrier regions G0 can be formed with well-known 18 ¦ ion implantation techniques. In the device configuration shown ~9 ¦ in FIG 17, charge is transferred from left to right by providing 20 ¦ two selected clock voltage signals 01' and 02 to the two series 21 ¦ of alternate electrodes as shown. Subsequent investigations 22 ¦ showed that poor transfer efficiency in this type of device 23 could be attrihuted to errors in the alignment of the implanted 24 barrier re'gions 60 with respect to the corresponding electrodes 54, as well as to the uncontrolled surface potential in the gap 26 between the electrodes 54. FIC 17 shows the desired alignment 27 between the electrodes 54 and the barrier regions 60 for left 28 to r-igh~ charge transfer.
29 A partial solution to the uncontrolled surface potential problem can be achieved by making the semiconductor region beneatl - - -. - ~-lZsO/I

1~7693~
I
. .
1 t:he gap formed between the electrodes 54 highly conductive.
2 Suc}l structurcs llave been referred to as C4D devices (Conductively 3 Coupled Charge Coupled Devices). This solution has the primary 4 disadvantage of storing only minimal charge in the highly con-

5 ductive regions, and therefore not being attractive for high-

6 density device applications. A more attractive solution to the

7 uncontrolled surface potential problem is achieved by making

8 the inter-electrode gap as I1arrow as possible. If the gap width

9 56 is reduced to submicron dimensions, it has been found that, for'

10 conventional device parameters, tihe effects of adjacent electrodes

11 effectively control the gap potential, even though the surface of

12 the ~ap itself is not covered by an electrode. Althou~h using

13 submicron gaps is a possible solution, the fabricatioll of devices

14 with such small geometries on a planar surface has heretofore not

15 been economically acceptable to the solid-state electronics

16 industry. It is possible to produce these small gap widths by

17 using electron-beam lithograpl1y, Y-ray lithography, or shadowing

18 techniques; however, these methods suffer from the drawbacks of

19 requiring equipment and processes not commonly used or readily

20 available in the solid-state electronics industry.

21 Various designs have been proposed to ensure that the barricr

22 regions ~0 in a two-phase, buried-channel, implanted-~arrier CCD

23 tructure align with the corresponding electrodes 54. Of the

24 esigns available, the most ~Jidely accepted is shown in FIG 18 and uses two overlapping levels of electrodes 6~ and 70. The 26 electrodes are formed from polycrystalline silico1l-~hicn has 27 been ni~hly doped with appropriatc i~,purities to render it con-28 ductive. To form the structure shown in FIG l8, n type impurities 29 are introduced into the upper surface of the substrate 50 using 3 ion implantation techniques to form the buried-channel region 58 ~..

l -- - F-123()/1 _ 1~769~4 An insulating layer of silicon dioxide 52 is then thermally 2 grown on tne upper surface o~ the substrate 50. ~n additional 3 insulating layer 62 of silicon nitride is then formed on the upper 4 surface of the insulating layer 52. T11e first layer of poly-silicon electrodes 64 are then formed 01l the upper surface of the 6 insulating silicon nitride layer 6Z as shown. An insulating 7 layer of silicon dioxide 68 is then thermally grown on the exposed 8 surfaces of the polysilicon electrodes 64 leaving a first level 9 inter-electrode gap 66. The first level of electrodes 64 are use~ as a mas~ during the ion implantatioh of p type impurities 11 to form the n- type ~arrier regions 60 aligned beneath tne first 12 level intér-electrode gaps 66. The second level of doped poly-13 silicon electrodes 70 are then overlappingly formed as shown 14 in the gaps 66 b~etween tne first level of electrodes 64, An insulating layer of silicon dioxide 72 is then thermally gro~n on 16 the exposed surfaces of the second level of electrodes 70.
17 Adjacent first and second level electrodes are then electrically 18 connected as shown to form a serics of composite electrodes 1g whicll are alternately connected to a pair of selected clock voltage signals 01 and 02.
.. .. .. .
21 There are at least three disadvantages to the CCD design 22 shown in FIG l~. First, the second level of conductors 70 23 necessarily overlap a portion of the first level of conductors 24 64. In devices for optical imagin~ where tlle image is trans-mitted through the conductor layers, this overlap reduces the 26 optical response of the device. Second, the minimum length of 27 a device made Wit}l this structure is limited by the required 28 alig1lmçn~ tolerancc to ensure overlap of the edges of the two 29 electrode levels 64 and 70, as well as by the minimum first level inter-electrode gap 6G which is commercially producible, For 31 instance, with present technolo~y, a two micron minimum alignment ~ SU/l .

1C~7693~

1 tolerance for each side of the second level of electrodes 70 2 is generally required, and a three micron first level inter-3 electrode gap 66 is a typical minimum width commercially producible. Therefore, the minimum cell size currently available (a "cell" in the two-phase structure comprises 6 two barrier regions 60 and two potential well regions between 7 the barrier regions) is 2û microns. A third disadvantage of 8 the two level CCD structure shown in FIG 18 is that each of 9 the second level of electrodes 70 ~barrier electrodesj must be externally connected to its associated adjacent first 11 level electrode 64 (potential well electrode). Tnis electrical 12 connection is usually done on anotner part of the device 13 structure, and generally requires more device area than would 14 be required for structures wherein the barrier electrode and the potential well electrode are integral.
16 A more detailed discussion of charge coupled devices is 17 given in an article entitled "Charge-Coupled Devices", by 18 G.F. Amelio which appeared on page 22 in the February 1974 19 issue of Scientific American.
Two examples of charge-coupled device structures are .......
21 provided which both embody and illustrate the edge etch 22 technique of the present invention. In the first example, 23 the edge etch technique is used to produce a two-phase 24 implanted barrier CCD structure having a single level of electrodes in which the disadvantages of a wide gap between 26 electrodes and possible implanted barrier region misalignment 27 are eliminated. It will be shown that by the elimination of 28 portion~.of this process, a single electrode level two-phase 29 buried-cha~nel implanted barrier structure may be produced in which the barrier electrode is separated from the potential - F-1230/l 1~)7693~

well electrode by a narrow gap. It will also be shown that 2 by elimination of further portions of the process a single 3 level electrode, multi-phase CCD can be produced in which the electrodes are separated by narrow gaps.
s¦ In the second example, a process is described in which 61 the edge etch technique of the invention is used to produce 71 a two-phase implanted barrier CCD structure having a first 8 ¦ and a second level of electrodes.
¦ In this second example both tne first level and second 10 ¦ level inter-electrode gaps are produced with the edge etch 11 ¦ technique. It will be shown that by the elimination of 12 ¦ certain portions of this process, a multi-phase CC~ having 13 ¦ two levels of electrodes is produced.

_ 278 ._. _ _ _ .

1076~3~

~YAiiPLE #l 2 Referring now to FIG 19a, a substrate lO0 is shown in 3 partial cross section and will be used as the starting material for this example. The substrate 100 comprises a wafer of mono-5 crystallille silicon about 500 microns thi~k (although other 6 thicknesses can also be used, if so desired) that nas been 7 boron-doped with approximately 5 x 1014 impurity atoms per cubic 8 centimeter, and hence is of p type conductivity. Although this 9 example uses a silicon semiconductor substrate, it will be evident~
10 to those skilled in the art that ot'ner semiconductor materials 11 capable of being used to make a charge-coupled device can be 12 used. Furthermore, it is to be understood that the regions of 13 specified conductivity type dcscribed in the text and shown 14 in the fi~ures of this application can be of opposite type conductivity, if so desired, in order to provide a CCD structure 16 Usil-g charge packets cor,lprising the opposite type minority 17 carrier.
18 An n type region 102 is formed on the surface portion of 19 the semiconductor substrate 100 using arsenic or phosphorous as the n type dopant for that region. Devices employing this n type ,.. ,. ...
21 layer arc referred to in the literature as "buricd-channel"
22 charge-coupled devices. The operation and function of a buried-23 chann21 regiol- such as region 102 is set forth in a paper ~y 24 C.~. Kim, J.~ ar1y, and G.F. Amelio, entitled "Buried Channel

25 Charge-Coupled Devices", presented at and published in the

26 proceeding of the ~lortheast Electron. Res. Eng. Meet. (~EREM),

27 Boston, Mass., !~ov. 1-3, l972.

28 I~ t~is example, tne n type region 102 has a thickness of

29 about 0.5 microns and a pnosphorous impurity level of approxi-

30 mately 3 x 1016 atoms per cubic centimeter.

()/1 1~7693~

1 i~ext, the substrate lO0 is coated with an appropriate insulating layer for CCD operation. In this example, the 3 insulating layer comprises a two-layered structure of silicon 4 nitride 10~ over silicon dioxide 104. The layer of silicon dioxide 104 is grown on the upper surface of the substrate 100 6 using well-known thermal oxidation techniques and is approxi-7 mately 800 Angstroms thick. The overlying layer of silicon 8 nitride 106 is formed on the upper surface o-f the layer 104 9 using well-known chemical vapor deposition techniques and is ' approximately ~00 Angstroms thick.
1l Next, a layer of electrically conductive material 108 12 (whicn will subsequently be subdivided using the edge etch 13 technique of the invention to form a plurality of individual 14 electrodes) is formed on the upper surface of the layer,of 15 siliconnitride 106. In this example, the layer 108 of poly-16 crystalline silicon is formed using well-known chemical vapor 17 deposition techniques. Layer 108 is hig'nly doped with 18 appropriate impurities to render it conductive and is approxi-19 mately 4000 Angstroms thick.
Next, a layer 110 of silicon nitride approximately 400 21 Angstroms thick is formed on the upper surface of the doped 22 polycrystalline silicon layer 10~.
23 Next, a 7500 Angstrom thick layer 112 of silicon dioxide 24 is formed OR the upper surface of the layer of silicon nitride 11~. The layer of silicon dioxide 112 is deposited by well-26 known chemical vapor deposition tecllniques and is hereinafter 27 referred to as vapox to distinguish it from thermally grown 28 silicon dioxide which is often referred to as thermox.
29 ~ext, a lOOn Angstrom thick layer 114 of silicon nitride is formed on the upper surface of tne silicon dioxide layer 112.

_ . ~ _ 1~76934 1 The layer of silicon nitride 114 is shown in FIG l9a with a 2 pair of apertures 116 and 118 which expose selected portions 3 of the layer of vapox 112. lhe apertures 116 and 118 in the layer of silicon nitride 114 are formed by photolithographic definition and etching techniques common to the semiconductor S industry. In this example, these apertures are approximately ~
7 5 microns wide and are disposed on 15 micron centers.
8 Referring now to FIG l9b, portions of the vapox layer 112 9 and the silicon nitride layer 110 lying in registration beneath the apertures 116 and 11~ have been removed. The exposed 11 portions of the vapox layer 112 are etched away with a buffered 12 hydrofluoric acid solution. Although other etchants can be 13 successfully employed, one acceptable solution for etclling 14 silicon dioxide comprises: 473 ml of 49% hydrofluoric acid (electronic grade); and 2832 ml of 40O aqueous ammonium 16 fluoride. At room temperature ~22C) this solution etches 17 approximately 25 Angstroms per second of densified vapor 18 deposited silicon dioxide (vapox) and approximately 17 Angstroms 19 per second of thermally grown silicon dioxide (thermox). It will be understood by those skilled in the art that these ...... .
21 typical etch rates are influenced by a variety of factors.
22 Among these factors are the level of impurities in the material 23 to be etclled and the geometry and location of the exposed 24 material. For example, when an etchant is used to remove material in a location where the flow of etchant is restricted, 26 some local depletion of the etchant and local saturation of 27 the solution with removed material can occur and hence the 28 etch ~at~ at the location of restricted flow can be somewhat 29 slowed. The subsequently exposed portions of the silicon nitride layer 110 are etched away with hot phosphoric acid.

~-1230/1 l ~76934 l ., I When 85% phosphoric acid (electronic grade) is used at 155C, 21 approximately 50 Angstroms per minute of silicon nitride are

31 etched. Care is taken to etch completely through the exposed ¦ portions of the silicon nitride layer 110 without completely s¦ etching the thicker silicon nitri~e layer 114. As a result 61 f etching through the silicon dioxide layer 112, lateral edges 71 120, 122, 124 and 126 are formed. In like manner, etching 81 through the silicon nitride layer 110 forms lateral edges 128, 9¦ 130, 132 and 134.
10¦ l~ell-known ion implantation techniques are next used to 11¦ form n- regions 136 and 138 in the n type region 102 in under-12¦ lying registration with the apertures 116 and 118. The ~31 remaining portions of the layers 114, 112 and 110 function to 14¦ protectively mask those portions of the n type region 102 that 15 ¦are to remain unaffected by the ion implant. Since this iOII
16 ¦implantation step is used to form n- type regions in the 17 ¦existing n type region 102, boron (or other desired p type) 18 ¦ions are used to convert the selected portions of the n type 19 ¦region 102 to n-type implante~ barrier regions 136 and 138.
20 ¦ Referring now to FIG l9c, the exposed lateral edges 120, 21 ¦122, 124 and 126 Oll the layer 112 of silicon dioxide are etched 22 la selected distance to form new lateral edges 140, 142, 144 23 ¦and 146 as shown. In this examplc, the distance between 24 ¦lateral edges 120, 122, 124 and 126 and new lateral edges 140, 142, 144 and 146 respectively is approximately 0.5 microns.
26 i~ext, as shown in FI~ l~d, the exposed portions of the 27 electrically conductive layer 108 of highly doped poly-28 crystallr~e silicon are thermally oxidized to form protective 29 layers 148 and 150 as shown. In this example, these layers of silicon dioxide 148 and 150 are grown to a thickness of r --~ 3U/4 I 1~)7693~

¦approximately 1500 Angstroms. The layers 143 and lS0 have 2 ¦lateral edges 152, 154, 156 and 15~ whicn are juxtaposed lateral 31 edges 128, 130 and lateral edges 132, 134 respectively. It i~
noted that silicon oxides can be thermally grown in ways well 5¦ known to tllose skilled in the art such that oxides do not for~
61 to any appreciable extent on silicon nitride. Accordingly, ~n 7 ¦this exar,lple, the growth of the thermox layers 148 and 150 does 8 ¦not preclude the selective etching of those portions of the 9 ¦layer 110 of silicon nitride exposed between the lateral edges 10 ¦152, 154, 156 and 158 on the layers 148 a~d 150 and the lateral 11 ¦edges 140, 142, 144 and 146 on the layer 112 respectively.
12 ¦ Referring now to FIG 19e, conventional deposition, photo-13 ¦lithographic dcfinition and etching processes similar to those 14 ¦described above are employed to protectively cover one side of 15 ¦the apertures 116 and 118 substantially as shown. In this 16 ¦example, the protective covering comprises a 400 Angstrom thick 17 ¦layer 160 of silicon nitride covered with a 2000 Angstrom thick 18 llayer 162 of vapox.
l9 ¦ Thereafter, as is shown in FIG 19f, the exposed lateral 20 ¦edes 12g and 132 on the layer 110 of silicon nitride are 21 etched to form new lateral ed~es 164 and 166 respectively.
22 The formation of these new lateral edges produces narrow openings 23 16~ and 170 to the surface of the layer 108 of highly doped 24 polycrystalline silicon. Although in this etch step a portion of the layers 114 and 160 are et~hed as shown, sufficient 26 portions of layer 160 remain to protect the lateral edges 130 27 and 134 from etching. The narrow openings 168 and 170 are 28 bounded hy the pairs of lateral edges 164, 152 and 166, 156 29 respectively. The widths of the narrow opcnings 168 and 170 are controllable by the location of the latcral ~dges 140 and .... . . ..... _ ,.,_ , _ ~ F-1230/l 107693~

144, and by the type, concentration, time and temperature of 2 the silicon nitride etchant used. In this example, as mentioned 3 above, the lateral edges 140 and 144 on the layer 112 of vapox have been laterally displaced by etching a distance of 5 approximately 0.5 microns.
6 i~ext, as is shown in FIG l9g, the exposed portions o~ the 7 electrically conductive layer 108 of polycrystalline silicon 8 lying beneath the narrow openings 168 and 170 are etched away 9 exposing portions of the insulating layer 106 of silicon lO nitride. This etching step cre~res a plurality of electrodes 11 176 formed from remaining portions of the electrically conduc-12 tive layer 108 of highly doped polycrystalline silicon which 13 are electrically isolated from similar adjacent electrodes by 14 inter-electrode gaps 172 and 174. It is to be understood that the exposed portions of polycrystalline silicon can be removed 16 with either well-known liquid chemical etchants or a plasma 17 etch. Althougll other etchants can be successfully employed, 18 one acceptable solution for etching polycrystalline silicon 19 comprises, by volume: 50 parts 70% nitric acid (electronic gra~e); 1 part 49% nydrofluoric acid (electronic grade); and ...... ..
21 20 parts deionized water. At room temperature ~22C), this 22 solution etches polycrystalline silicon at a rate of approxi-23 mately 80 Angstromsper second. In this example, the width of 24 the resulting inter-electrode gaps 172 and 174 is approximately 0.5 microns. As described above, in a two-phase CCD alternate 26 electrodes 176 are electrically connected. This electrical 27 interconnectioll can be accomplished by appropriately patterning 28 and etch~ng the layer lOS, or by a subsequent intcrconnection.
29 Thcreafter, the remainill~ portions of layer 162, 160, 114, 112 and 110 together with the thermally oxidized regions 148 l;~ U/ l 1~76934 and 150 are removed, leaving the structure s}-own i~ FIG 19h.
21 FIG l9h shows a portion of the insulating layer 106 of 3 silicon nitride lying in regiStratioJI beneath tlle inter-4 electrode gaps 172 and 174 removed. lhe removal of a portion of the layer 106 follows as a natural consequence of removing 61 the silicon nitride layers 160, 114, and 110. lhe thicknesses 71 of the various layers of silicon nitride are selected such that 81 the partial etching of tne layer 106 does not adversely affect 9I the operation of the CCD. , 10¦ Referring now to FIG l9i, the inter-electrode gaps 172 and 11¦ 174 are used as windows through which n type impurity atoms ,21 are introduced to form electrically conductive n+ regions 178 ~31 and 180 in the n type region 102. In tllis example, well-known 14¦ ion implantation techniques are used to introduce phosphorous ~51 impurity atoms through the insulating layers 106 and 104, while 16 using the remaining portions of the layer 108 of polycrystalline 17 ¦silicon as a protective mask. It is to be understood that 18 ¦standard diffusion processes can also be used to form the n+
19 ¦regions 178 and 180.
20 I With reference now to FIG 19j, a passivating layer 182 21 ¦is formed to seal the surface of the electrodes 176 as well as 22 ¦the inter-electrode gaps 172 and 174. In this example, the 23 ¦passivating layer comprises approximately 2000 ~ngstroms of 24 ¦silicon dioxide (ther~.ox) grown on the exposed surfaces of the 25 ¦layer 108 followed by tlle vapor deposition of approximately 26 5000 Angstroms of vapox.
27 The final structure shown in FIG l9j formed by the process 28 describe~.above is a single-level-electrode, buried channel, 29 implanted-barrier CCD. In this structure the electrodes are essentially planar and are separated by narrow gaps. Moreover, __~ , .. .

¦ F-123u/1 l 1~76934 ¦ that portion of the buried channel region beneath the narrow 2¦ gaps is highly conductive. ~urthermore, eacll barrier electrode 31 and its associated potential well electrode are formed from a single piece of conductive material. Lastly, the implanted 51 barrier regions are essentially aligned with their corresponding 6¦ electrodes.
71 Those skilled in the art of CCD structure and fabrication ¦ will understand that deletions of various portions of the 9¦ processing steps described above can be made to produce devices lO¦ with substantially different characteristics than those pro-ll ¦duced with the described process. In particular, the step l2 ¦used to produce the highly doped n+ regions 178 and 1~0 can be 13 ¦eliminated and will result in a two phase implanted-barrier 14 ¦CCD in which the control of the potential beneath the inter-l5 ¦electrode gaps 172 and 174 is achieved solely by the minimized 16 ¦widths of these gaps. ~loreover, the steps used to form the 17 ¦silicon nitride layer 160 and the vapox layer 162 which protec-18 ¦tively cover one side of the apertures 116 and 118 as shown 19 ¦in FIG 19e can be deleted. Such deletion will produce a CC~
20 ¦in which the barrier electrodes are separated by narrow gaps 21 ¦fro~ the potential well electrodes. In such a device, two-22 ¦phase operation is obtained by electrically connecting adjacent 23 barrier and potential well electrodes. This connection may be 24 accomplished permanently as part of the device structure.
25 Alternatively, the electrodes can be selectively connectable 26 so that the device can be made to transfer charge left or right, 27 dependillg upon the order of the connection of the barrier 28 and p~tel~ial well electrodes. ~limination of the step used 29 to form the n type buricd channel region 102 will result in a 30 surface-channcl CCD. ~dditionally, the elimination of the ¦ F-lZ30/1 I ~07693~

~¦ ~teps used to form the n- type in~planted barrier regions 136 21 and 138 will result in the fabrication of a multi-phase CCD.
31 Referring again to FIG l9g, it is not necessary to 41 completely etch the exposed portions of the polycrystalline I silicon layer 108 to form electrically isolating interelectrode 6 gaps 172 and 174. In the example given above where the 71 electrically conductive layer 108 of highly doped polycrystalline 81 silicon was approximately 4000 Angstroms thick, etching only 9¦ 3000 An~stroms of this layer followed by the thermal growth 10¦ of a passivation layer 182 of thermox approximately 2000 11¦ Angstroms thick will convert all of the unetched polycrystalline 12¦ silicon in the interelectrode gaps 172 and 174 to nonconductive 13¦ silicon dioxide. This nonconductive material will serve to 14¦ electrically isolate the adjacent electrodes.
15¦ Greater control over the potential in the semiconductor 16¦ regions lying in registration beneath the narrow inter-,71 electrode gaps 172 and 174 can be achieved by the deposition 18¦ of a layer of electrically conductive material (not shown) on ~9¦ the upper surface of the passivating layer 182 of silicon 20¦ dioxide. Such a layer of electrically conductive material Zl¦ can be electrostatically biased to provide absolute control 22¦ over the potential in regions beneath the interelectrode gaps 231 172 and 174. The application of such an overlying conductive 241 layer does.not affect the planarity of the CCD surface. If 251 the CCD is not to be used as an imaging device, the remaining 26¦ portions of the layers 162, 160, 114, 112, 110, 148 and 150 as 271 shown in FIG l9g need not be removed as these layers do not 28 ¦ detrimentally affect the electrical performance of devices 29 I produced with this process.

~ . ~ _ ¦ F-lZ30/1 I iO76934 Il EXA~PLE #2 I , ~¦ Referring now to FIG 20a a substrate 200 is shown in 3¦ partial cross-section an~ will be used as the starting material 41 for this example. The substrate 200 co~prises a wafer of 5¦ monocrystalline silicon about 500 microns thick that has been 61 boron doped witn approximately 5 x lOl4 impurity atoms per 71 cubic centimeter, and hence is of p type conductivity. Although 81 this example uses a 500 micron thick silicon semiconductor 9 ¦substrate, it will be evident to those skilled in the art 10¦ that other semiconductor materials of appropriate thicknesses 11 ¦in wl~ich charge coupled devices can be formed may be used.
12 ¦Furthermore, it is to be understood that the regions of specified 13 ¦conductivity type described in the text and shown in the figures 14 ¦of this example can be of opposite type conductivity, if so 15 ¦desired, to provide a minimum geometry overlapping gate CCD
16 ¦structure using charge packets comprising the opposite typc 17 ¦minority carrier.
18 ¦ An n type region 202 is formed on a portion of the surface 19 ¦of the semiconductor substrate 200 using arsenic or phosphorous 20 ¦as the n type dopant for that region. Devices cmploying this 21 In type layer are rcferred to in the literature as "Buried Channel"
22 ¦char~e-coupled devices. In this example, the n type region 202 23 ¦nas a thickness of about 0.5 microns and a phosphorous impurity 24 level of approximately 3 x lO16 atoms per cubic centimeter.
~ext, the substrate 200 is coated with an appropriate 26 insulating layer for CCD operation. In this example, the 27 insulating layer comprises a two-layered structure of silicon - 28 nitride ~6 over silicon dioxide 204. The layer of silicon 29 dioxide 204 is grown on the upper surface of the substrate 200 using well-known ther~.al oxidation techniques and is approxi-. , . . _ _ ¦ r~ -107693~

mately 800 Angstroms thick. Tne overlying layer of silicon 2 nitride 206 is formed on the upper surface of the layer 204 3 using equally well-Xnown chemical vapor deposition techniques and is approximately 900 Angstroms thick.
l~ext, a layer of electrically conductive material 208 6 ~which ~ill subsequently be subdivided using the edge etch 7 technique of the invention to form a plurality of individual 8 first-levcl electrodes also referred to as potential-well 9 electrodes) is formed on the upper surface of the layer of 10 silicon nitride 206. In this example, the layer 208 is formed ll from polycrystalline silicon which has been highly doped with l2 phosphorous impurities to render it conductive and is approxi-13 mately 4000 Angstroms thick.
14 Next, a layer 210 of silicon nitride approximately~400 An~stroms thick is formed on the upper surface of the dope~
16 polycrystalline silicon layer 208.
~ ext, a 7500 Angstrom thick layer 212 of silicon dioxide 18 is formed on the upper surface of the layer of silicon nitride 19 210. The layer of silicon dioxide 212 (vapox) is deposited vy well-known chemical vapor deposition tcchniques.
21 i~ext,- a 1000 Angstrom thick layer 214 of silicon nitride 22 is formed on the upper surface of the silicon dioxide layer 212.
23 The layer of silicon nitride 214 is shown in FIG 23 witn a pair 24 of apertures 216 and 21~ which expose selected portions of tne layer of vapox 212. The apertures 216 and 218 and the layer of 26 silicon nitride 214 are formed by photolithographic dcfinition 27 and etching techniques common to the semiconductor industry.
28 In th}s cxample these apertures are approxir,lately 3 microns wide 29 and are disposed on 10 micron centers.
Referring now to FIG 20b, portions of the vapox layer 212 ¦ F-1230/1 :1~7693~ , I an~ the silicon nitride layer 210 lying in registration beneath 2 the apertures 216 and 218 have been removed. The exposed 3 portions of the vapox layer 212 are etched away with a buffered hydrofluoric acid solution. The subse~uently exposed portions S of the silicon nitride layer 210 are etc'ned away with hot 6 phosphoric acid. T~ie thicknesses of the layers 214 and 210 7 have been chosen sucn that it is possible to etch completely 8 through the exposed portions of the silicon nitride layer 210 9 without completely etching the thicker silicon nitride layer 214. As a result of etciling througll the silicon dioxide layer ll 212, lateral edges 220, 222, 224, and 226 are formed. In like l2 ¦manner, etching through the silicon nitride layer 210 forms l3 lateral edges 22~, 230, 232 and 234.
14 Referring now to ~IG 20c, the exposed lateral edges 220, 222, 224 and 226 on the layer 21Z of silicon dioxide ~vapox) l6 are etched a selected distance to form new lateral edges 240, 17 242, 244 and 246 as shown. In this example, the distance 18 between lateral eages 220, 222, 224 and 226 and new lateral 19 edges 240, 242, 244 and 246 respectively is approximately 2.0 20 microns.
.....
21 .~ext, as shownin ~IG 20d, the exposed portions of the 22 electrically conductive layer 208 of highly doped polycrystalline 23 silicon are thermally oxized to form protective layers 248 and 24 250. In this example, these layers of silicon dioxide 248 and 250 are grown to a thic~ness of approximately 1500 Angstroms.
26 The layers 248 and 250 have lateral edges 252, 254, 256 and 27 25~ wllich are juxtaposed lateral edges 22~, 230 and lateral edges 28 232, 254~~aspectively. As noted above, the growth of the 29 thermox layers 248 and 250 does not prcclude the selective 3 etching of those portions of the layer 210 of silicon nitride ~_ .. .. . . . . . .. . . .

l;~ U/l . ln76s34 1 exposed between the lateral cdges 252, 254,256 and 258 on the 2 layers 248 and 250 and the lateral edges 240, 242, 244 and 246 3 on the layer 212 respectively.
4 Thereafter, as is shown in FIG 20e, the exposed lateral 5 edges 22E, 230, 232 and 234 on the layer 210 of silicon nitride 6 are etche~ to form new lateral edges 260, 262, 264 and 266 7 respectively. The formation of these new lateral edges defines 8 -narrow openings 26~, 270, 272 and 274 to the surface of the 9 layer 208 of highly doped polycrystalline silicon. The narrow opening 268 is bounded by a pair of lateral edges 260 and 252 11 as shown. The other simultaneously formed narrow openings are 12 'oowlded in like manner. The width of tllese narrow openings are 13 controllal)le by the location of the lateral edges 240, 242, 244 l4 and 246 and by the type, concentration, time and temperature of the silicon nitridc etchant used. In this example, as mentioned 16 above, the lateral edges 240, 242, 244 and 246 on the layer 212 17 of vapox have been laterally displaced by etchin~ a distance of 18 approximately 2.0 microns.
l9 i~ext, as is shown in FIG 20f, the exposed portions of the electrically conductive layer 20~ of highly doped polycrystalline 21 silicon lying beneath the narrow openings 268, 270, 272 and 274 22 are etched away exposing portions of the insulating layer 206 23 of silicon nitride.. This etching step creates a plurality of 24 first level-potential well electrodes 276 formed from remaining portions of the electrically conductive layer 20~ of highly 26 dope~ polycrystalline silicon which are isolated from similar 27 adjacent electrodes by a plurality of first level interelectrode 28 gaps ~78~ It is to be understood that the exposed portions of 29 layer 208 of polycrystalline silicon can be removed with well-known chemical etchants or a plasma etch. In this example, the _-- _ _ ~ - . . . .

l F-1230/1 1 ~0~6934 ¦widths of tne resulting interelectrode gaps 278 are approximately 21 2.0 microns.
31 Thereafter, the remaining portion of layers 214, 212 and 210 ¦ together l~ith the layers 24~ and 250 are removed leaving the 51 structure substantially as shown in FIG 20g. This figure shows 61 a portion of the insulating layer 206 of silicon nitri~e lying 71 in registration beneath the first level interelectrode gaps 278 81 removed. The removal of a portion of the layer 206 follows as 9¦ a natural consequence of removing the silicon nitride layers 214 10¦ and 210. In this example, the thicknesses of the various layers ll¦ of silicon nitride have been selected such that t}le removal of 12¦ the layers 214, 212 and 210 together with the layers 248 and 250 13¦ does not completely remove the layer 206 from the interelectrode 14¦ gap regions. Referring now to FIG 20h, a passivating layer 280 15¦ is formed on the exposed portions of the plurality of first level 16¦ potential well electrodes 276 as shown. In this example, the 17¦ passivating layer 280 preferably comprises approximately 3000 18¦ Angstroms of thermally grown silicon dioxide (thermox). The l9¦ passivating layer 2~0 is grown in such a way that the exposed 20¦ portions of the layer 206 of silicon nitride are not oxidized 21¦ to any appreciable extent.
22¦ .~ext, well-known ion implantations techniques are used to 231 form a plurality of n- regions 282 in the n type region 202 in 24 ¦underlying registration with the plurality of first level inter-25 ¦electrode gaps 278. The plurality of first level electro~es 26 ¦276 together with each electrode-'s associa~ed layer of thermox 27 ¦function to protectively mask those portions of the n type 28 ¦regio~.20~.tllat are to remain unaffected by the ion implant.
29 ¦Since this ion implantation step is used to form n- type regions 30 ¦in the existing n type region 202, boron (or other desired p type) r F-1230/l l ions are used to convert the selected portions of tne n type 2 region 202 to n- type implanted barrier regions.
3 i~ext, as shown in FIG 20i, a layer of electrically conduc-tive material 308 (which will subsequently be subdivided using 5 the edge etch technique of the invention to form a plurality of 6 individual second level barrier region electrodes) is formed in 7 the first level interelectrode gaps 278 and on the surface of 81 the insulating thermox layer 280 as shown. In this example, the 9¦ layer 308 is formed using well-known vapor deposition techniques , 10¦ from polycrystalline silicon which has been highly doped Witil ll ¦approprlate impurities to render it conductive and is approxi-12 ~mately 4000 Angstroms thick.
I3 l 14 ¦ l~ext, a layer 310 of silicon nitride approximately.400 15 ¦Angstroms thick is formed on the ul)per surface of tne highly l6 ¦doped electrically conductive polycrystalline silicon layer 308.
17 ¦ ~ext, a 7500 Angstrom thick layer 312 of silicon dioxide l8 ¦is formed on the upper surface of the layer of silicon nitride 19 ¦310. The layer of silicon dioxide 312 is deposited by well-20 ¦known chemical vapor deposition techniques.
21 I ~ext, a layer of silicon nitride 314 approximately 1000 22 ¦Angstroms thick is formed on the upper surface of the vapox 23 ¦layer 312. The layer of silicon nitride 314 shown in FIG 20i 24 is provided with a pair of apertures 316 and 318 which expose selected portions of the underlying layer of vapox 312. lhe 26 apertures 316 and 318 in the layer of silicon nitride 314 are 27 formed by photolithographic definition and etching tec'nniques 28 conmlon t~ tlle semiconductor industry. These apertures are 29 centered above alternate first level interelectrode gaps 278, 30 are approximately 4 microns wide and are disposed on 10 micron ~ _ ~ , , . . _ 107693~

1 centers.
2 Referring now to ~IG 20j, portions of the vapox layer 312 3 and the silicon nitride layer 310 lying in registration beneath the apertures 316 and 318 have been removed. The exposed 5 portions of the vapox layer 312 are etclled with a buffered 6 hydrofluoric acid solution. Tne subsequently exposed portions 7 of the silicon nitride layer 310 are etched away Wit}l hot 8 phosphoric acid. Care is taken to etch completely through the 9 exposed portions of the silicon nitride layer 310 Wit]lOUt com-10 pletely etching the thic~er silicon nitride layer 314. As a 11 result of etching through the silicon dioxide layer 312, lateral 12 edges 320, 322, 324 and 326 are formed. In like manner, etching 13 through the silicon nitride layer 310 forms lateral edges 328, 14 330, 332 and 334. `
Referring now to FIG 20k, the exposed lateral edges 320, 16 322, 324 and 326 on the layer 312 of silicon dioxide (vapox) are 17 etched a selected distance to form new lateral edges 340, 342, 18 344 and 346 as shown. In this example,tne distance between 19 lateral edges 320, 322, 324 and 326 and new lateral ed~es 340, 342, 344 and 346 respectively is approximately 1 micron.
21 ~ext, as shown in ~IG 201, the exposed portions of the 22 electrically conductive layer 308 of highly doped polycrystalline 23 silicon are thermally oxidized to form protective layers 348 and 24 350 as shown. In this example, these layers of silicon dioxide 348 and 350 are grown to a thick~ess of approximately 1500 26 ngstroms. The layers 348 and 350 have lateral edges 352, 354, 27 356 and 358 which are juxtaposed lateral edges 328, 330 and - 28 lat~ral e~ges 332, 334 respectively. ~s noted above, the 29 growth of the thermox layers 348 and 350 does not preclude the 30 etching of those portions of the layer 310 of silicon nitride ___. , ~!

I l;-lZ3()/1 I

I la76s34 ¦ exposed between the lateral edges 352, 354, 356 and 358 on the 21 layers 348 and 350 and the lateral edges 340, 342, 344 and 346 31 on the layer 312 of vapox respectively.
4 Thereafter, as is shown in ~IG 20m, the exposed lateral S edges 328, 330, 332 and 334 on the layer 310 of silicon nitride 6 are etched to form new lateral edges 360, 362, 364 and 366 7 respectively. The formation of these new lateral edges define 8 narrow openings 368, 370, 372, and 374 to the surface of the gI layer 308 of highly doped and electrically conductive poly-10¦ crystalline silicon. The narrow opening 368 is bounded by a 11¦ pair of lateral edges s60 and 352 as shown. The other simul-12¦ taneously formed narrow openings are bounded in like manner.
13 ¦The widt}l of these narro~ openings are controllable by the locatio 14 ¦of the lateral edges 340, 342, 344 and 346 and by the type, con-15 ¦centration, time and temperature of the silicon nitride etchant 16 ¦used. In t~is example, as mentioned above, the lateral edges 17 1340, 342, 344 and 346 on the layer 312 of vapox have been 18 ¦laterally displaced by etching a selected distance of approxi-l9 ¦mately 1 micron. ~ext, as is shown in FIG 20n, the exposed 20 ¦portions of the electrically conductive layer 308 of highly 21 ¦doped polycrystalline silicon lying beneath the narrow openings 22 ¦368, 370, 372 and 374 are etched away exposing portions of the 23 ¦insulating layer 280 of silicon dioxide. This etching step 24 ¦creates a plurality of second level barrier electrodes 376 formed from remaining portions of the electrically conductive ~6 layer 308 of highly doped polycrystalline silicon whicll are 27 isolated from similar adjacent electrodes by a plurality of 28 second.l~vel interelectrode gaps 378. It is again to be under-29 stood that the exposed portions of the layer 308 of poly-30 crystalline silicon can be removed with well-known li~uid cilemical i _ ..

--- F-1230/1 _ 1~76934 I etchants or a plasma etch. In this example, the widtlls of the 2 resulting second level interelectrode gaps 378 are approximately 3 1 micron. Thereafter, the remainillg portions of layers 314, 312 and 310 together with the layers 348 and 350 are removed leaving S the structure substantially as shown in FIG 20O. This figure 6 shows a portion of the passivating layer 280 of tllermox lying 7 in registration beneath the plurality of second level inter-8 electrode gaps 378 removed. The removal of a portion of the 9 layer 280 follows as a natural consequence of removing the 10 silicon dioxide layer 312 together with the layers 34g and 350.
11 The removal of a portion or all of the passivating layer 280 of 12 vapox lying beneath the second level interelectrode gaps 378 13 is not critical as it will be regrown in the final process step.
14 Lastly, as is snown in FIG 20p, a passivating layer 380 is formed to seal the exposed surfaces of the second level 16 electrodes 376 and the exposed portions of the first level 17 electrodes 276 lying beneath the second level interelectrode 18 gaps 37~. In this example, the passivating layer 380 comprises 19 approximately 2000 An~stroms of silicon dioxide (tnermox) grown on all exposed polycrystalline silicon surfaces followed 21 by the vapor deposition of approximately5000 Angstroms of vapox.
22 The first and second levels of electrodes 276 and 376 are 23 electrically connected as described above for two-phase CCD
24 operation. Those skilled in the art of CCD structure and fabri-cation will un~erstand that deletion of various portions of the 26 processing steps described in this example can be made to pro-27 duce devices with substantially aifferent characteristics than 28 those pr~uced with the described process. In particular, 29 eliminatioll of the step used to form the n type buried channel region 202 will result in a surface channel CCD. Additionally, ~; ,-.

I F-1G~U/1 l 1~76934 the elimination of the steps used to form the n- type implanted 2 barrier regions 282 will result in the fabrication of a multî- .
3 phase CCD. Moreover, standard photolithographic definition 4 and etching processes can be used to form either the first or second level interelectrode gaps 278 and 378 respectively, if 6 so desired, with the remaining gap being produced Wit}l the edge ~
7 etch technique of the invention.
/// //

19 .

~ l ~229 _._ ~ . . ,; ;. ._ 1(~76939L

MINI~IUM GEOMETRY LATERAL ISOLATIO~
2 Many ways are known to provide lateral electrical isolation 3 for a plurality of regions of conductive material used in semi-con~uctor devices. Among these ways are appropriately biased 5 PN junctions described in U.S. Patent ~o. 3,117,26~ issued to 6 i~oyce on January 7, 1964. Combinations of pn junctions and zones 7 of intrillsic and extrinsic semiconcluctor materials can also 8 ¦be employed and are described in U.S. Patent No. 3,150,299 issued 9 ¦to Noyce on September 22, 1964. Dielectric isolation techniques , 10 ¦are taught in U.S. Patent No. 3,3(Jl,023 issued to Frescura on 11 ¦July 2, 1968. Mesa etching to ac'nieve lateral isolation is 12 Idiscussed in U.S. Patent ~o. 3,4~9,961 issued to Frescura, et al, 13 ~on January 13, 1970. Tucker and Berry in U.S. Patent l~o. 3,736,19 14 ¦issued ~lay 29, 1973 disclose the use of selectively doped poly-15 ¦crystalline silicon to help isolate islands of single crystal 16 ¦silicon in whicih circuit elements can be formed. U.S. Patent 17 ¦~o. 3,64~,125 issued to D.L. Petlzer on March 7, 1972 teaches ho 18 la thin silicon epitaxial layer, formed on a silicon substrate, 19 ¦is sub-divided into electrically isolated pockets by a grid of 20 ¦oxidized regions of epitaxial silicon material which extends 21 ¦through tlle epitaxial layer to a laterally extending pn junction.
22 ¦ In tlle commercial exploitation of ma~y of the above 23 ¦mentioned isolation techniques, it is necessary to provide opening 24 ¦to the surface of a semiconductor material for use as cither etch 25 ¦or diffusion windows. In each of these isolation techniques it 26 ¦is possible, in principle, to use openings with sub-micron 27 ¦geometries and in so doing reduce the overall size of the devices 28 being_.pr~duced. In practice, however, for reasons given above, 29 it has heretofore not been possible to use such minimum geometry isolation techniques in commercially viaole operations.

1 1~7693~
I ¦ The advantages available in reducing the widtn of isolation 21 regions and therefore reducing device size in integrated circuit 31 manufacturin~ are substantial. First, tne cost of processing a 41 single semiconductor wafer depends very little on tlle number of 5¦ devices W]liC]I tne wafer contains. Therefore, the cost per device 61 can be reduced by making the devices smaller and therefore having 71 more devices per semiconductor wafer. Second, the yield (number 81 of good devices on a waer) on semiconductor wafers decreases 9¦ drastically witn increasing device size. This decrease is due , 10¦ primarily to defects which appear in both the scr,liconductor 11 ¦wafers and to defects which are caused by processing and photo-12 ¦masking 5teps. Since the cost per device is directly related to 13 ¦yiel~, it is desirable to minimize device size in order to maxi-14 ¦mize yield. Tllird, it is clear that practical limits on device 15 ¦size exist witll present integrated circuit manufacturing tech-16 ¦niques. Although this limit is becoming larger as technology 17 ¦develops, it has not kept pace with the demands for devices which 18 ¦provide more complex circuit functions on a single structure. A
19 ¦reduction in lateral isolation dimensions will help a~eviate this 20 ¦space problem ~y providing more available active area on a device 21 ¦of a given size, allowing added design flexibility and more com-22 ¦plex circuit function within the device size limitations of 23 present day technology.
24 Two sp-ecific examples follow which show utility of the edge etch technique of the invention in providing narrow lateral 26 isolation areas of silicon dioxide in semiconductor devices.
27 ~xample 3 l~roduces lateral isolation of a polysilicon film via 28 the t~ler~al growth of silicon dioxide beneatll a plurality of 29 narrow openings in an overlying layer. Example 4 provides an illustration of the utility of thc edge etch techllique of the ... ,,.., ___ ~

F-123~/l ~6 ~ 3 ~

1 invention in subdivision of a thin silicon epitaxial layer 2 formed on a mono-crystalline silicon substrate to form semi- .
3 conductor structures such as tnosc tau~ht by Peltzer in the 4 U.S. Patent cited above.
~s!/""

19 . .

l2 26 .

- 28 _. _ ~0 _ _ ~

~~ - 1-12~0/1 1~)76934 1 EXA~PLE ~3 2 Referring now to FIG 21a, a substrate 400 is showli in partial 3 cross-section alld will be used as the starting material for this example. The substrate 400 compri~ses a wafer of mono-crystalline silicon about 500 microns thick. Although this exarr.ple uses a 6 silicon semiconductor substrate, it will be evident to those 7 skilled in the art that other materials of ot'ner tllick]lesses can 8 be used. Furthermore, although unspecified in this example, the 9 semiconductor substrate 400 can be of either p or n type conduc-tivity if so desired depending upon the type of impurity atoms 11 used as do?ants.
12 ~ext, a layer of insulating rmaterial 402 is formed on the 13 upper surface of the substrate 400. In this example, tlle insu-14 lating layer comprises approxima~bly 1200 Angstroms of ~thermally grown silicon dioxide (thermox). .~ext, a layer of electrically 16 conductive material 404 is formed on the upper surface of the 17 ¦layer of thermox 402. In this example, the layer 404 is formed 18 using well-known vapor deposition techniques from polycrystalline 19 silicon which has been highly doped with appropriate impurities to render it conductive and is approximately 3000 Angstroms thick.
21 ;~arrow oxide regions extending from the upper surface of this 22 polysilicon layer to the uppcr surface of the layer 402 of 23 thermox will subse~uently be formed ~subdividing the layer 404 24 into laterally isolated regions.
Thercafter, a thin layer 406 of thermox is grown on the 26 upper surface of the layer 404 of doped polycrystalline silicon.
27 This laycr is appro;~imately 500 Angstroms thick.
- 28 ~e~, a layer 408 of silicon nitride approximately 1500 2g Angstroms thick is formed on the upper surface of the thin layer 406 of thermox.

_-._ ¦ ~ F-1230/l 1 107~i934 1 ¦ ~ell-known chemical vapor deposition techniques are employed 2 ¦to form a 3000 Angstrom tnick layer 410 of polysilicon on the 3 ¦upper surface of the layer 408. Because this layer of poly-¦ silicon will subsequently be completely removed it need not be 5¦ electrically conductive and hence is not doped with impurity 61 atoms.
7 ¦ Thereafter, a layer 4i2 of silicon nitride approximately 8 ~1000 Angstroms thick is formed on the upper surface of the undoped 9 ¦polycrystalline silicon layer 410. , 10 ¦ To complete the initial structure shown in ~IG 21a a 2000 ll ¦Angstrom tnick layer of silicon dioxide 414 is deposited by well-12 ¦known chemical vapor techniques on the upper surface of the layer 13 ¦of silicon nitride 412. As narrow oxide isolation regions are 14 ¦to be thermally grown in tlle doped polysilicon layer 404 at lS la p~urality of locations 416, 41~, 420 and 422, the vapox layer 16 ¦414 is provided with apcrtures 424 and 426 as shown. These 17 ¦apertures are formed by photolithographic definition and etching 18 ¦techlliques common to the semiconductor industry. Associate~
19 ¦with aperture 424 are two lateral edges 428 and 430. Likewise, 20 ¦aperture 426 has associated with it a pair of lateral edges 432 ...... ~
21 ¦and 434. These lateral eclges are each disposed in overlying 22 ¦registration along a selected edge of a to-be-ormed narrow 23 ¦lateral oxide isolation region as will be fully understood from 24 the detailed description herei;lbelow.
Referring now to FIG 21b, the exposed portions of the 26 silicon nitride layer 412 lying in registration beneath the 27 apertures 424 and 426 are etched away with hot phosphoric acid.
.28 This etc~ing of the silicon nitride layer 412 results in the 29 forr~lation of lateral ed~es 436, 43~, 440 ancl 442 as shown.
.~ext, as s'nown in ~IG 21c, the exposed portions of the layer r ~-12sO/l 410 of undope~ polycrystalline silicon are thermally oxidized 2 to form protective layers 444 and 446. In this example, these 3 protective layers of thermo~ are grown to a tllic~lless of approximately 1500 Angstroms. The layers 444 and 446 have 5 lateral edges 448, 450, 452 and 454 which are juxtaposed the 6 lateral edges 436, 438, 440 and 442 respectively. Again, the 7 growth of the thermox layers 444 and 446 does not preclude the 8 selective etching of the exposed lateral edges 436, 438, 440 and 9 442 on the layer 412 of silicon nitride.
~ext, as is shown in FIG 21~, the exposed lateral edges ll 436, 438, 440 and 442 on the layer 412 of silicon nitride are 12 etched to for~ new lateral edges 456, 458, 460 and 462 respectively .
13 The formation of these new lateral edges define narrow openings 14 to the surface of the layer 410 of undoped polycrystalline silicon at the locations 416, 418, 4Z0 and 422 respectively. As can be 16 seen in the figure the narrow opening at the location 416 is 17 bounded by the newly formed lateral edge 456 on the layer 412 18 of silicon nitride and the lateral edge 44& on the protective l9 layer of thermox 444. The other simultaneously formed narrow openings are similarly bounded. The width of these narrow opening 21 are a function of the degree to which the layer 412 of silicon 22 nitride is laterally etched. In this example, the narrow 23 openings are approximately 0.5 microns wide.
24 Next, as is shown in ~IG 21e, the exposed portions of the undoped polysilicon layer 410 lying in registration beneath the 26 narrow opcnings at the locations- 415, 418, 420 and 422 are etche~
27 away. l`hereafter, the remaining portions of the layer of vapox 28 414, t~he-layer of silicon nitride 412, together with the protectiv 29 layers of therll~ox 444 and 44G are removed leaving the structure substantially as sllown i31 FIG 21f. FIG 21f shows a portion of ~r~ ~~ .~, ` _ ~-123~/1 1~376~34 1 the silicon nitride layer 408 lying in registration beneath the 2 narrow openings 416, 418, 420 and 422 removed. The removal of 3 a portion of the layer 408 follows as a natural consequence of 4 removing silicon nitride layer 412. The removal of this portion of layer 438 does not adversely affect the final structure of this 6 process.
7 Referring now to FIG 21g, the remaining portions of the 8 exposed silicon nitride layer 408 lying in registration beneath 9 the narrow openings atthe locations 416, 418, 420 and 422 are 10 etched away. I~aving formed narrow openings in the layer 408 of 11 silicon nitride at the locations 416, 418, 420 and 422 the 12 remaining portions of the layer 410 of undoped polycrystalline 13 silicon are removed. The etchant used to remove the remaining 14 portions of the layer 410 does not etch the layer 404 of~ elec-15 trically conductive higllly doped polycrystalline silicon because 16 of the presence of the thin layer 406 of thermox. Subsequently, 17 as silown in ~IG 21h, the exposed portions of the thin layer 406 18 of thermox lying in registration beneath the narrow openings in 19 the layer 408 of silicon nitride at the locations 416, 41~, 420 20 ¦and 422 are etcned away. This etching exposes portions of the 21 electrically conductive layer 404 of highly dope~ polycrystalline 22 silicon. As a rule of thumb, the thermal growth of one unit of 23 silicon dioxide on a silicon surface consumes approximately 0.45 24 units of silicon material. Therefore, approximately 1000 Angstroms f thè exposed surface of the highly doped polysilicon layer 404 26 re etched away as shown in FIG 21h. This partial etching of the 27 olysilicon layer is done to provide a more nearly planar surface 28 n the--re~ultillg final structure as will be describea below.
29 ;~ext, the exposed portions of the electrically conductive ighly-dol)ed polysilicon layer 404 are thermally oxidized formillg 31 solation regions 464, 4G6, 468 and 470 at .the locations 416, 418, 1 -1G~V/ 1 1~}76934 1 420 and 422 respectively as is sho~n in FIG 21i. This step 2 subdivides and laterally electrically isolates selected portions 3 472, 474 and 476 of tlle layer 404.
Lastly, the remaining portions of the silicon nitride layer 40~ and the tllin thermox layer 406 are removed leaving the struc-6 ture substantially as shown in FIG 21j. ~ecause of the partial 7 etchi-llg in a previous step of a portion of the layer 404, and the removal by etching of the thin thermox layer 406, tne oxide-9 isolation regio-.ls 464, 466, 468 and 470 protrude only slightly above the upper surface of the layer 404 ieaving that surface ll substantially planar.
12 Those skilled in the art of semiconductor structure fabri-13 cation will understand that deletions of various portions of the 14 processing steps described above can be made to produce`struc-tures different from those described. In particular, the step 16 of partially etching the exposed surface of the layer 404 as 17 shown in Fig. 21h may be eliminated with the result of having a 18 step of approximately 3000 Angstroms in tne final structure.
19 This step neigllt will not adversely affect the usefulness of this structure in most applications.
2~

28 . _:

_. ~ _ ~-1230/1 1C~7693~

1 ~-XA~LE #4 2 This example of minimum ~eometry lateral isolation, which 3 both embodies and further illustrates the process and structure of the in~ention, is provided to show specific applicability of 5 the Edge Etch Technique to the subject matter tau~ht by U.S.
6 Patcnt No. 3,648,125 en~itled: "~lethod of ~al~ricatin~ Integrated 7 Circuits with Oxidized Isolation and the Resulting Structure"
8¦ issued to Dou~las L. Peltzer on ~larch 7, 1972. In this example, I a thin silicon epitaxial layer, formed on a silicon substrate is 10¦ subdivided into electrically isolated pockets by a grid of oxi-11¦ dized re~ions of epitaxial silicon material (hereafter called 12¦ "Oxidized Isolation Re~ions"). These regions are oxidized 13 ¦through the epitaxial layer to a lnterally extending isolation pn 14 ¦junction (hercafter called the "Isolation pn Junction")~
15 ¦ Referring now to ~IG 22a, a substrate 500 is sholYn in 16 ¦partial cross section and will be used as the starting material 17 ¦for this example. The substrate 500 comnrises a ~afer of mono-18 ¦crystalline silicon that has been boron doped wi~h approximately 19 15 x 1014 impurity atoms per cubic centimeter, and hence is of 20 ¦P type conductivity. ~ext, a thin silicon epitaxial layer 504 21 ¦approximately l.25 microns thick is formed on the upper surface 22 ¦of the substrate 500. In this example, the epitaxial layer is 23 ¦doped ~itll approximately 3 x l016 phosphorous impurity atoMs per 24 ¦cubic centiineter and hence is of n type conductivity. The 25 ¦metallurgical interface bet~een the epitaxial silicon layer 504 26 ¦and the u11derlying silicon substrate 500 is denoted by a line 502.
27 ¦Usually, the resultant isolation pn junction is not coextensive wi h 28 the meta~lurgical interface 502. Rather, during the formation 29 of the epitaxial layer, the position of the isolation pn junction is determined by dopant concentrations, diffusion constants, and .~- , . _ process parameters. Its ultimate position is also influenced by the subsequent processing of the substrate. However, for pur-poses of this description, it is assumed that the isolation pn junction is coextensive with the metallurgical interface 502.
Moreover, it is to be understood that the substrate 500 can be of opposite conductivity type if the conductivity type of the thin silicon epitaxial layer is also reversed.
Next, a mask layer 506 of silicon nitride is formed on the upper surface of the epitaxial layer 504. The layer 506 is formed using well-known chemical vapor deposition techniques and is approximately 1000 Angstroms thick.
Thereafter, a layer 508 of aluminum oxide is formed on the upper surface of the layer 506. In this example, the layer of aluminum oxide is formed using standard RF sputtering techniques and is approximately 2000 Angstroms thick.
To complete the initial structure shown in Figure 22a, a 400 Angstrom thick layer 510 of silicon nitride is deposited by well-known chemical vapor techniques on the upper surface of the layer 508 of aluminum oxide. As narrow oxidized isolation regions are to be thermally grown in the thin silicon epitaxial layer 504 extending downwardly through the isolation pn junction at a plurality of locations 512, 514, 516 and 518, the nitride layer 510 is provided with apertures 520 and 522 as shown. These apertures are formed by photolithographic definition and etching techniques common to the semiconductor industry. Associated with the aperture 520 are two lateral edges 524 and 526. Like-wise, the aperture 522 has associated with it a pair of lateral edges 528 and 530. These lateral edges are each disposed in overlying registration along a selected edge of a to-be-formed narrow oxidized isolation region as will be fully understood from the , ~-123U/l 1~76~34 1 detailed description hereinbelow.
2 Referring now to FIG 221~, the exposed portion of the aluminun 3 oxide layer 508 lying in registration beneatl1 the apertures 520 4 and 522 are etched away. Although other etchants can be success-5 fully employed, one acceptable etchant for aluminum oxide com-6 prises, by volume: 3 parts 49% hydrofluoric acid ~electronic ~
7 grade); 2 parts 70% nitric acid (electronic grade); and 60 parts 8 deionized water. At room temperature (22C),this solution etches 9 alur,linum oxide at a rate of ap~roximately 5 to lO Angstroms per I0 second. This etching of the aluminum oxide layer 508 results in 11 the formation of lateral edges 532, 534, 5s6 and 5~8 as shown.
12 ~éxt, as can be seen by reference to FIG 22c, a thin layer 13 540 of silicon dioxide (thermox) is thermally grown on the 14 exposed surfaces of the layer of silicon nitride 510. Simul-taneously, the exposed portions of the silicon nitride layer 506 16 lying in re~istration beneatl1 the apertures 520 and 522 are 17 thermally oxidized to form protective layers 542 and 544 respec-18 tively. In this example, the layers of thermally grown silicon 19 dioxide 540, 542 an~ 544 are approximately lO0 An~stroms thick.
As has been noted in previous examples, the 100 Al1gstrom thick-....... ,.
21 ness of silicon dioxide produced on the silicon nitride layer 540 22 is negligible when com~ared to the amount of silicon dioxide pro-23 duced by the same process on polycrystalline silicon (typically 24 8000 An~str~ms). 11owever, this thin layer is sufficient for protecting the silicon nitride layer 540 in the present ap~
26 cation.
27 The layers 542 and 544 have lateral edges, 546, 548, 550 and - 28 552 wh.ic~.are juxtaposed the lateral edges 532, 534, 536 and 538 29 respectively. It is noted that the characteristics of aluminum oxide do not change to any appreciable extent under the process ., . .. .. . _ ~76939~

I conditions necessary to form silicon oxide on the surface of 2 silicon nitride. Accordingly, in this example, the growth of the 3 protective thermox layers 542 and 544 does'not preclude selective etching o the exposed lateral edges 532, 5a4, 536 and 538 on the S layer 50~ of aluminum oxide.
6 Referring now to ~IG 22d, the exposed lateral edges 532, 534, 7 536 and 538 on the layer of aluminum oxide are etched to form new 8 lateral edges 554, 556, 558 and 560 respectively. In this example 9 it is assumed that the lateral edges Sa2, 534, 535 and 538 are etched with hot phosphoric acid. Since this solution also etches 11 silicon nitride (but at a slower etch rate), the exposed edges 12 of silicon nitride layers 506 and 510 are shown as also being 13 etched in FIG 22d. The formation of the new lateral edges 554, 14 556, 55~ and 560 defines narrow o~enings to the layer 506 of silicon nitride at the locations 512, 514, 516 and 51~ respectivel .
16 As can be seen in the figure, the narrow opelling at the location 17 512 is bounded by the newly formed lateral edge 554 on the layer 18 508 of aluminum oxide and the lateral edge 546 on the protective 19 layer 542 of thermox. The other simultaneously formed narrow openings are similarly bounded. The widths of these narrow 21 openings are a function of the de~ree to which the layer 508 22 of aluminum oxide is laterally etched. In tllis example, the 23 narrow openings are approximately 1.5 microns wide. ~ext, as is 24 sho~m in ri-g. 22e, the exposed portions of the silicon nitride layer 506 lying in registration beneath the narrow openings at 26 the locations 512, 514, 516 and 513 are removed by plasma etching.
27 As a rule of thumb, the thermal growth of one unit of silicon - 28 dioxi~e ~n a silicon surface consumes approximately 0.45 units of 29 silicon material. Thercfore, to provide for a more nearly planar surface in the resulting final'structure, approximately 0.7 micron ~- , . _ ~.,,~ ~,.. _~

107693~

1 of the thin silicon epitaxial layer 504 lying exposed in regis-tration beneat]l the narrow openings in tne layer 506 of silicon 3 nitride at the locations 512, 514, 516 and 518 are etched away.
~ext, the exposed portions of the thin silicon epitaxial layer 5 504 are thermally oxidized forming oxidized isolation regions 6 562, 564, 566 and 568 at the locations 512, 514, 516 and 518 7 respectively as is shown in FIG 22f. It is to be noted that 8 the oxidized isolation regions 562, 564, 566 and 568 extend 9 downwardly past the isolation pn junction which for purposes 10 of ~his description is assumed to be at the same location as 11 the metallurgical interface 502. This step subdivides and 12 laterally electrically isolates pockets of epitaxial silicon 13 material 570, 572 and 574. Each such pocket of epitaxial 14 silicon is isolated by a portion of the isolation pn junction and portions of the oxidized isolation regions. Moreover, each 16 such pocket can contain active devices, passive devices, or both.
17 Cross-under regions of low resistivity can be for]ned in the lB substrate to interconnect regions separated by at least one 19 oxidized isolation region. .
Lastly, the remaining portions of the thermox layers 540, ...... . .
21 542 and 544 together with the aluminum oxide laycr 508 and the 22 silicon nitride layers 510 and 506 are removed leaving the 23 structure substantially as shown in FIG 22g. The top surfaces 24 of the thin silicon epitaxial layer 504 and the oxidized isolation regions 562, 564, 566 and 568 are substantially 26 co-planar, thereby reducing undesirable elevation variances 27 or "steps"
28 ///i/ . _ ~ . - _ _ . I'-l~su/l 10~69~

1 EXAMPLE #5 2 In the fabrication oE integrated circuits, one device require-3 ment is to provide interconnections between various individual circuit elements. Such interconnections are usually made by 5 employing a metalization layer. This layer may comprise, for 6 example, such materials as gold, aluminum, or polycrystalline 7 silicon. In semiconductor devices manufactured with present 8 day technology, a significant portion of the space required for 9 such metalization patterns is taken up by the spacing between 10 metal lines. In many device applications it is possible, in 11 principle, to make these metal interconnect lines with spacings 12 between them of a~proximately l micron without degradation of 13 device ~erformance. In practice, however, it has heretofore not 14 been possible to use such minimum geometry metalization~gaps in commercially viable devices. The reason for this is because of 16 the difficulties in producing such narrow geometry openings in the 17 metalization layer. As noted above, it is possible to produce 18 narrow openings using electron beam lithography, A-ray lithography 19 or shadowing techniques. However, again as outlined in more detail above, these methods suffer from thc drawback of requiring 21 equipmcnt and processes not commonly usel or readily available to 22 the solid state electronics industry.
23 The advantages to be realized from a reduction in spacin~
24 bet~Jeen metalization lines and the attcndant reduction in overall device size in integrated circuit manufacturing are substantial.
26 First, the cost of processin~ a single semiconductor wafer depends 27 very little on the number of devices which the wafer contains.
-28 There~ore? the cost per device can be reduced by making the 29 devices smaller and thereforc having more devices per semicon-ductor wafer. Second, the yield ~number of good devices on a _ .,"~ ......... _ ~,--........ ~

~ I-12~/1 .' 1~76934 11 ~afer) on semiconductor wafers decreases drastically with increas-21 ing device size. This decrease is due primarily to defects which 3 ap~ear in both the semiconductor wafers and to dcfects which are ¦ caused by processing and photo maskin~ steps. Since the cost per 51 device is directly related to yield, it is desirable to minimize 6¦ device size in order to maximize yield. Third, it is clear that 71 practical limits on device size exist with present integrated ¦circuit manufacturing techniques. Although this limit is becoming 9¦ larger as technology develops, it has not kept pace with the 10 ¦demands for ~evices which provide more complex circuit functions 11 ¦on a single structure. A reduction in spacing required between 12 ¦metalization lines will allow for closer spacing of active device 13 ¦com~onents which will result in greater design flexibility and 14 ¦more complex circuit functions witnin dcvice size limitations of 15 ¦present tcchnology.
16 ¦ In this example, a process is described for producing narrow 17 ¦ga~s in a metalization layer using the edge etch technique of 18 ¦the invention. These narrow gaps electrically isolate the resul-19 ~ting metal interconnection lines from one another. In addition 20 ¦to the many advantages associated with providing smaller geometrie 21 for existing integrated circuits, other applications of a minimum 22 geometry metalization gap structure can be envisioned. For exampl , 23 in high frequency integrated circuit applications, one important 24 design consideration is the reduction of electrical coupling between adjacent metalization lines. By using the narrow metaliza 26 tion gaps produced l~ith the edge etch technique of the invention, 27 it is possible to provide a metal round plane between 28 active metalization lincs without using any more device arca 29 than is used ~or the ga~ between the metal conductors on present devices.

- ~ ~
` ~-1230/1 1(~7693~

1 Although this example relates to semiconductor integrated 2 circuit manufacturing, it will be understood by those skilled 3 in the art that there are other alternate application areas.
4 For instance, the process of this example can be applied to 51 patterning printed circuit boards with higher packing density 61 than presently available.
71 Referring now to FIG 23a, a semiconductor body 600 is 81 shown in partial cross-section and will be used as the starting 9¦ material for this example. The semiconductor body 600 comprises 10¦ a wafer of mono-crystalline silicon on which all of the steps 11¦ necessary to produce a useful integrated circuit device have 12¦ been performed up to the step of supplying metal interconnects 13¦ between individual circuit components. Therefore, much of the 14 ¦upper surface of the semiconductor body 600 is covered with an 13 ¦insulating layer of silicon dioxide which is provided with a 16 ¦plurality of windows through which electrical connection can 17 ¦be made to selected underlying individual circuit components.
18 ¦This electrical connection is made by adherently forming an 19 ¦electrically conductive layer 602 on the upper surface of the 20 ¦semiconductor body 600. In tllis example, the layer 602 com-21 ¦prises approximately 8000 Angstror,ls of gold which has been 22 ¦deposited using well-known evaporation techniques.
23 ¦ Next, as shown in FIG 23~, a layer 612 comprising a poly-24 imideenamel such as Pyre M.L. (registered Trademark of 25 ¦E.I. Du Pont De Nemours and Company) is fo~med on the upper 26 ¦surface of the gold layer 602. In this example, tne polyimide 27 layer 612 is approximately one micron thick. A decided advantage 28 of using this material for thislayer is that it may be applied 29 and prepared for use without requiring temperatures in excess of approximately 250C.

~ F-1230/1 l 1~7693~

~¦ i~ext, a plurality of masks 614 and 616 are formed on the 21 upper surface of the polyimide layer 612. In this example, the 31 masks 614 and 616 are formed from a 0.75 micron thick layer of ¦ photoresist which has been photolithographically defined and 51 subsequently etched. Associated with the mask 614 of photo-6¦ resist are two lateral edges 618 and 620. Likewise, the mask 71 616 llas associated with it a pair of lateral edges 622 and 624.
81 These lateral edges are each disposed in overlying registration 9¦ along a selected edge of a to-be-formed narrow gap in the under-10¦ lying gold layer 602 at locations 604, 606, 608 and 610 as will 11¦ be fully understood from the detailed description hereinbelow.
12 ¦ Réferring now to FIG 23c, the exposed portions of the 13 ¦polyimide enamel layer 612 are etched away with hydrazine 14 ¦exposing portions of the layer 602 of gold. This etching process 15 ¦results in the formation of lateral eages 630, 632, 634 and 636 16 ¦disposed along and below the lateral edges 618, 620, 622 and 17 ¦624 respectively on the photoresist masks 614 and 616.
18 ¦ ~ext, as can be seen by referenced FIG 23d, a thin layer 19 ¦638 of nickel is electrolytically deposited on the exposed 20 ¦portions of the layer 602 of gold. In~this example, the layer . ,.. ,. .
21 ¦of nickel is approximately 3000 Angstroms thick. Alternatively, 22 ¦the layer of nickel may be deposited by vacuum evaporation 23 ¦techniques common to the semiconductor industry. In this case, 24 it is essential that the nickel layer 638 be discontinued over the step between the exposed surface portions of the gold layer 26 602 and the upper surfaces of mask regions 614 and 616. The ~7 layer of nickel 638 has lateral edges 640, 642, 644 and 646 28 juxtaposed lateral edges 630, 632, 634 and 636 respectively on 29 the remaining portion of the polyimide layer 612.
Next, as shown in FIG 23e, thc exposed lateral edges 630, Y. ,,,, , . ~
r~..~. ..

F-lZ30/l 107693~

1 632, 634 and 636 on the laycr 612 of polyimide enamel are 2 etched to form new lateral edges 648, 650, 652 and 654 3 respectively. The formation of these new lateral edges 4 defines narrow openings to the surface of the layer 602 of gold at the locations 604, 606, 608 and 610 respectively.
6 As can be seen in FIG 23e, the narrow opening at the location 7 604 is bounded by the newly formed lateral edge 648 on the 8 layer 612 of polyimide enamel and the lateral edge 640 on 9 the layer of nickel 638. The other simultaneously formed narrow openings are similarly bounded. The width of the 11 narrow openings are a function of the degree to which the 12 layer 612 of polyimide enamel is laterally etched. In this 13 example, the narrow openings are approximately 2.0 microns 14 wide. ~
Thereafter, as shown in FIG 23f the exposed portions of 16 the layer 602 of gold lying in registration beneath the narrow 17 openings at the locations 604, 606, 608 and 610 are removed 18 with a cyanide etching solution to form a plurality of indivi-19 dual electrical conductors 656 separated by narrow gaps. In this example, the narrow gaps are approximately 2.0 microns 21 wide.
22 Next, the remaining portion of the polyimide enamel layer 23 612 togetner with the photoresist masks 614 and 616 are removed 24 leaving the structure substantially as shown in FIG 23g. If so desired, the nickel layer 638 can also be removed leaving 26 the structure substantially as shown in FIG 23h. These final 27 structures provide a plurality of individual electrical 28 conductors separated by narrow gaps.

7 ~ ___ . _ F-1~3~/1 ._ 107693~

1 From the foregoing detailed description it will be 2 evident that there are a number of changes, adaptations and .
31 modifications of the present invention which come within tlle ¦ province of those skilled in the art; however, it is intended 5¦ that all such variations not departing from the spirit of 61 the invention be considered as within the scope thereof as 71 limited solely by the appended claims.
/////

7 ¦ I

224 ~ .

.

~~ ~ ._

Claims (2)

THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:

1. A planar process for producing a charge-coupled device of the type having a single level of electrodes separated from one another by narrow gaps comprising the steps of: forming an electrically insulating layer on a substantially planar surface of a semiconductor substrate;
forming an electrically conductive layer on the upper surface of said electrically insulating layer; forming a plurality of narrow interelectrode gaps in said electrically conductive layer, each interelectrode gap being formed by a process comprising the steps of; forming on a portion of said electrically conductive layer an etchable mask having a first narrow-open-ing-forming lateral edge disposed along a selected edge of the to-be-formed interelectrode gap; forming a protective layer of a material possessing a set of etch characteristics different from etch characteristics of said electrically conductive layer on the adjacent exposed surface of said elec-trically conductive layer, said protective layer being formed at a thickness substantially less than the thickness of said etchable mask and with a second narrow-opening-forming lateral edge contiguous to and juxtaposed said first narrow-opening-forming lateral edge; etching said first narrow-opening-forming lateral edge on said mask to expose an unprotected portion of said electrically conductive layer to produce a narrow opening to the surface of said electrically conductive layer; and, etching said electrical-ly conductive layer through said narrow opening and down to said electrical-ly insulating layer to thereby form one of said narrow interelectrode gaps.

2. The planar process of claim 1 wherein said electrically conductive layer comprises doped polycrystalline silicon.