DE2618445C2 - Verfahren zum Herstellen eines bipolaren Transistors - Google Patents

Verfahren zum Herstellen eines bipolaren Transistors

Info

Publication number
DE2618445C2
DE2618445C2 DE2618445A DE2618445A DE2618445C2 DE 2618445 C2 DE2618445 C2 DE 2618445C2 DE 2618445 A DE2618445 A DE 2618445A DE 2618445 A DE2618445 A DE 2618445A DE 2618445 C2 DE2618445 C2 DE 2618445C2
Authority
DE
Germany
Prior art keywords
layer
window
electrode
polycrystalline silicon
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE2618445A
Other languages
German (de)
English (en)
Other versions
DE2618445A1 (de
Inventor
Katsuyuki Dipl.-Ing. Yokohama Inayoshi
Yoshinobu Dipl.-Ing. Kawasaki Kanagawa Monma
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of DE2618445A1 publication Critical patent/DE2618445A1/de
Application granted granted Critical
Publication of DE2618445C2 publication Critical patent/DE2618445C2/de
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D10/00—Bipolar junction transistors [BJT]
    • H10D10/01—Manufacture or treatment
    • H10D64/0113—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0112—Integrating together multiple components covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating multiple BJTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H10P14/60—
    • H10P32/1414—
    • H10P32/171—
    • H10P95/00—
    • H10W20/01—
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/038—Diffusions-staged
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/106—Masks, special
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/123—Polycrystalline diffuse anneal
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/138—Roughened surface
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/914—Doping
    • Y10S438/923—Diffusion through a layer

Landscapes

  • Bipolar Transistors (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Cold Cathode And The Manufacture (AREA)
DE2618445A 1975-04-30 1976-04-27 Verfahren zum Herstellen eines bipolaren Transistors Expired DE2618445C2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP50051521A JPS51127682A (en) 1975-04-30 1975-04-30 Manufacturing process of semiconductor device

Publications (2)

Publication Number Publication Date
DE2618445A1 DE2618445A1 (de) 1976-11-18
DE2618445C2 true DE2618445C2 (de) 1986-10-16

Family

ID=12889304

Family Applications (1)

Application Number Title Priority Date Filing Date
DE2618445A Expired DE2618445C2 (de) 1975-04-30 1976-04-27 Verfahren zum Herstellen eines bipolaren Transistors

Country Status (6)

Country Link
US (1) US4125426A (enExample)
JP (1) JPS51127682A (enExample)
CA (1) CA1050667A (enExample)
DE (1) DE2618445C2 (enExample)
GB (1) GB1506066A (enExample)
NL (1) NL186478C (enExample)

Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4157269A (en) * 1978-06-06 1979-06-05 International Business Machines Corporation Utilizing polysilicon diffusion sources and special masking techniques
CA1129118A (en) * 1978-07-19 1982-08-03 Tetsushi Sakai Semiconductor devices and method of manufacturing the same
US4230522A (en) * 1978-12-26 1980-10-28 Rockwell International Corporation PNAF Etchant for aluminum and silicon
JPS55102266A (en) * 1979-01-31 1980-08-05 Fujitsu Ltd Fabricating method of semiconductor device
JPS6043656B2 (ja) * 1979-06-06 1985-09-30 株式会社東芝 半導体装置の製造方法
US4452645A (en) * 1979-11-13 1984-06-05 International Business Machines Corporation Method of making emitter regions by implantation through a non-monocrystalline layer
JPS56115525A (en) * 1980-02-18 1981-09-10 Chiyou Lsi Gijutsu Kenkyu Kumiai Manufacture of semiconductor device
US4411708A (en) * 1980-08-25 1983-10-25 Trw Inc. Method of making precision doped polysilicon vertical ballast resistors by multiple implantations
JPS5775453A (en) * 1980-10-29 1982-05-12 Fujitsu Ltd Semiconductor device and manufacture thereof
JPS57132357A (en) * 1981-02-10 1982-08-16 Oki Electric Ind Co Ltd Manufacture of semiconductor element
JPS5860569A (ja) * 1981-10-06 1983-04-11 Fujitsu Ltd 半導体装置の製造方法
US4437897A (en) 1982-05-18 1984-03-20 International Business Machines Corporation Fabrication process for a shallow emitter/base transistor using same polycrystalline layer
US4516145A (en) * 1983-08-31 1985-05-07 Storage Technology Partners Reduction of contact resistance in CMOS integrated circuit chips and the product thereof
JPS60126869A (ja) * 1983-12-13 1985-07-06 Matsushita Electric Ind Co Ltd 半導体装置の製造方法
US4665424A (en) * 1984-03-30 1987-05-12 Mitsubishi Denki Kabushiki Kaisha Semiconductor device
JPH0611053B2 (ja) * 1984-12-20 1994-02-09 三菱電機株式会社 半導体装置の製造方法
EP0193934B1 (en) * 1985-03-07 1993-07-21 Kabushiki Kaisha Toshiba Semiconductor integreated circuit device and method of manufacturing the same
US5280188A (en) * 1985-03-07 1994-01-18 Kabushiki Kaisha Toshiba Method of manufacturing a semiconductor integrated circuit device having at least one bipolar transistor and a plurality of MOS transistors
US4717678A (en) * 1986-03-07 1988-01-05 International Business Machines Corporation Method of forming self-aligned P contact
KR890005885A (ko) * 1987-09-26 1989-05-17 강진구 바이폴라 트랜지스터의 제조방법
US5204276A (en) * 1988-12-06 1993-04-20 Kabushiki Kaisha Toshiba Method of manufacturing semiconductor device
JPH0817180B2 (ja) * 1989-06-27 1996-02-21 株式会社東芝 半導体装置の製造方法
JPH05102175A (ja) * 1991-10-07 1993-04-23 Sharp Corp 半導体装置の製造方法
JP2001332561A (ja) * 2000-05-22 2001-11-30 Nec Corp バイポーラトランジスタおよびその製造方法
DE10229081B4 (de) * 2002-06-28 2007-07-19 Contitech Luftfedersysteme Gmbh Verfahren zum Trennen von Schläuchen und Vorrichtung zur Durchführung des Verfahrens
DE102007043614B3 (de) 2007-09-13 2008-11-20 Biocrates Life Sciences Gmbh Halterung für ein Trägermittel zum Einsetzen in eine zylinderförmige Öffnung
CN113053736B (zh) * 2021-03-11 2024-05-03 捷捷半导体有限公司 一种半导体器件制作方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3764409A (en) * 1969-09-29 1973-10-09 Hitachi Ltd Method for fabricating a semiconductor component for a semiconductor circuit
US3759762A (en) * 1970-10-19 1973-09-18 Motorola Inc Method of forming integrated circuits utilizing low resistance valueslow temperature deposited oxides and shallow junctions
US3719535A (en) * 1970-12-21 1973-03-06 Motorola Inc Hyperfine geometry devices and method for their fabrication
JPS5538823B2 (enExample) * 1971-12-22 1980-10-07
US3867216A (en) * 1972-05-12 1975-02-18 Adir Jacob Process and material for manufacturing semiconductor devices
US3847687A (en) * 1972-11-15 1974-11-12 Motorola Inc Methods of forming self aligned transistor structure having polycrystalline contacts
JPS5317393B2 (enExample) * 1973-01-16 1978-06-08
US3928081A (en) * 1973-10-26 1975-12-23 Signetics Corp Method for fabricating semiconductor devices using composite mask and ion implantation

Also Published As

Publication number Publication date
NL186478C (nl) 1990-12-03
US4125426A (en) 1978-11-14
GB1506066A (en) 1978-04-05
DE2618445A1 (de) 1976-11-18
NL7604632A (nl) 1976-11-02
CA1050667A (en) 1979-03-13
JPS51127682A (en) 1976-11-06
JPS5524703B2 (enExample) 1980-07-01
NL186478B (nl) 1990-07-02

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Legal Events

Date Code Title Description
8128 New person/name/address of the agent

Representative=s name: REINLAENDER, C., DIPL.-ING. DR.-ING., PAT.-ANW., 8

D2 Grant after examination
8364 No opposition during term of opposition