DE2612718A1 - Rechner-prozessor - Google Patents
Rechner-prozessorInfo
- Publication number
- DE2612718A1 DE2612718A1 DE19762612718 DE2612718A DE2612718A1 DE 2612718 A1 DE2612718 A1 DE 2612718A1 DE 19762612718 DE19762612718 DE 19762612718 DE 2612718 A DE2612718 A DE 2612718A DE 2612718 A1 DE2612718 A1 DE 2612718A1
- Authority
- DE
- Germany
- Prior art keywords
- input
- output
- circuit
- result
- sign
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
- G06F7/72—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using residue arithmetic
- G06F7/729—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using residue arithmetic using representation by a residue number system
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Mathematical Analysis (AREA)
- Mathematical Optimization (AREA)
- Pure & Applied Mathematics (AREA)
- Computational Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Computing Systems (AREA)
- Mathematical Physics (AREA)
- General Engineering & Computer Science (AREA)
- Complex Calculations (AREA)
- Executing Machine-Instructions (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| SU752114927A SU601689A1 (ru) | 1975-03-25 | 1975-03-25 | Арифметическое устройство |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| DE2612718A1 true DE2612718A1 (de) | 1976-10-07 |
Family
ID=20613181
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DE19762612718 Ceased DE2612718A1 (de) | 1975-03-25 | 1976-03-25 | Rechner-prozessor |
Country Status (4)
| Country | Link |
|---|---|
| DE (1) | DE2612718A1 (enExample) |
| FR (1) | FR2305783A1 (enExample) |
| GB (1) | GB1507121A (enExample) |
| SU (1) | SU601689A1 (enExample) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4121298A (en) * | 1976-04-30 | 1978-10-17 | Institut Matematiki I Mekhaniki Akademii Nauk Kazakhskoi Ssr | Central processing unit for numbers represented in the system of residual classes |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110750232B (zh) * | 2019-10-17 | 2023-06-20 | 电子科技大学 | 一种基于sram的并行乘加装置 |
-
1975
- 1975-03-25 SU SU752114927A patent/SU601689A1/ru active
-
1976
- 1976-03-23 GB GB1162176A patent/GB1507121A/en not_active Expired
- 1976-03-25 FR FR7608739A patent/FR2305783A1/fr active Granted
- 1976-03-25 DE DE19762612718 patent/DE2612718A1/de not_active Ceased
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4121298A (en) * | 1976-04-30 | 1978-10-17 | Institut Matematiki I Mekhaniki Akademii Nauk Kazakhskoi Ssr | Central processing unit for numbers represented in the system of residual classes |
Also Published As
| Publication number | Publication date |
|---|---|
| FR2305783A1 (fr) | 1976-10-22 |
| FR2305783B1 (enExample) | 1979-04-20 |
| SU601689A1 (ru) | 1978-04-05 |
| GB1507121A (en) | 1978-04-12 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| DE2353421C3 (de) | Elektronischer Rechner | |
| DE2058612A1 (de) | Verfahren und Schaltung zur Bildung eine Reziprowertes | |
| DE2934971A1 (de) | Datenverarbeitungssystem | |
| DE2930441C2 (de) | Anzeigeeinrichtung zur wahlweisen dynamischen oder statischen Anzeige | |
| DE1162111B (de) | Gleitkomma-Recheneinrichtung | |
| DE1549477B1 (de) | Einrichtung zur schnellen akkumulation einer anzahl mehr stelliger binaerer operanden | |
| DE2623986A1 (de) | Parallelrechenwerk | |
| DE68924386T2 (de) | Verfahren und Gerät zur Radix-2**n-Division mit überlappender Quotientenbitauswahl und gleichzeitiger Rundung und Korrektur des Quotienten. | |
| DE2612750A1 (de) | Multipliziereinrichtung | |
| DE10013068C2 (de) | Potenzierungsoperationsvorrichtung | |
| DE2405858A1 (de) | Normalisierendes verschiebezaehlernetzwerk | |
| DE2619307A1 (de) | Multipliziereinrichtung | |
| DE1549508A1 (de) | Logistische Anordnung zum Durchfuehren von arithmetischen Rechenoperationen,die zu einem positiven oder negativen UEbertrag fuehren | |
| DE2310553A1 (de) | Vorrichtung zur durchfuehrung arithmetischer und logischer operationen | |
| DE2513181A1 (de) | Elektronischer rechner | |
| DE2612718A1 (de) | Rechner-prozessor | |
| DE2039228A1 (de) | Verfahren und Vorrichtung zum Konvertieren und Stellenwert-Verschieben von Zahlsignalen unterschiedlicher Codes in einer Datenverarbeitungsanlage | |
| DE2727051B2 (de) | Einrichtung zur binären Multiplikation einer ersten Zahl als Multiplikand mit einer den Multiplikator ergebenden Summe aus einer zweiten und dritten Zahl im Binärcode | |
| DE2712582C2 (de) | DDA-Rechner (Digital-Differential-Analysator) | |
| DE1524197B1 (de) | Aritmetisch-logische einheit | |
| DE2539245C2 (enExample) | ||
| DE1965830B2 (de) | Vorrichtung zur Eingabe einer Dezimalzahl mit wählbarer Kommastelle in eine Rechenmaschine | |
| DE1524143B2 (de) | Arithmetisch-logische Einheit | |
| DE1090885B (de) | Parallel arbeitende, synchrone, elektrische, binaerrechnende Zahlenrechenmaschine, welche die Operation x+yz selbsttaetig auszufuehren vermag | |
| DE1524143C (de) | Arithmetisch logische Einheit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| 8131 | Rejection |