GB1507121A - Processor of computer - Google Patents

Abstract

1507121 Data processing INST MATE. MATIKI I MEKHANIKI AKAD NAUK KAZAKH SSR 23 March 1976 [25 March 1975] 11621/76 Heading G4A Two operands supplied to registers 1 and 2 and each represented by the remainders when the operand is divided by a plurality of relatively prime bases are processed by a system including a multiplier 38, a divider 39, a shifter 40 for shifting the second operand, and a modular arithmetic unit 7 for carrying out multiplications, subtractions and additions within the range (equal to the product of the bases) of the number representation; an analysis system 18 receiving inputs from registers 12, 13 containing the signs of the operands, and other inputs as shown provides the sign of the result to a register 29 and whether the result has overflowed (exceeded the range) to a register 58. The operand registers 1, 2 are connected to formers 32, 33 each of which form a representation of the value of the operand in a positional (e.g. decimal) notation. During additions, using the modular arithmetic unit 7, an analysis unit (74, Fig. 2, not shown) in the analysis system 18 provides the required outputs to registers 29 and 58 and a control signal to the arithmetic unit 7. During multiplications and divisions, using the arithmetic unit 7, the multiplier 38, or the divider 39, the sign of the result is derived from a modulo two adder (77, Fig. 2, not shown) in the analysis system 18 receiving the signs of the two operands. During shifting of the second operand by the shifter 40 the sign of the second operand is transferred to register 29 and an output of shifter 40 indicating whether an overflow has occurred is connected to register 58.