DE2612718A1 - COMPUTER PROCESSOR - Google Patents

Description

Patent Attorneys DJpl.-lng. R. B E ETZ sen. Dipl.-Ing. K. LAMPRECHT Dr.-Ing. R. B E E T Z Jr.

f »OOü Munich 22

Steinsdorfstrasse 1O

Tel. (0 89) 2272O1 / 227244 / 29B91O

Telegr. Allpatent Munich Telex B22O48

530-25.393P

March 25, 1976

Institut matematiki i mekhaniki Akademii Nauk Kazakhskoi SSR

Alma-Ata - USSR

Computer processor

The invention relates to a device for performing operations in a computer system (for short
Computer) and relates in particular to a computer processor that is represented in the residual class system
Operand works.

As is well known, the construction of a computer on the basis of a processor working in the residual class system allows to increase the performance of the computer.

-HdSl

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However, in order to create a general-purpose computer based on a processor operating in the residual class system the execution of all operations without restriction of the output operands required.

A computer processor is known (see SU Inventor's Certificate 419 891 from April 6, 1972) that is included in the residual class system operands shown, which has:

Register of a first and a second signed operand, the input of which is connected to a rail of the first resp. connected to the second operand, a module arithmetic unit whose inputs are connected to the outputs of the registers of the first and second operands, a control rail and the output of the module arithmetic unit are connected, while an output with the input of the module arithmetic unit in connection, a register for the result with sign, from which the one input with the output of the module arithmetic unit and the other input with the second output of the analysis system is connected, while the output is via a result output circuit with a result rail and the output of the result output circuit with the third output of the analysis system connected is.

The analysis system comprises a control circuit and a control circuit, the first outputs of which via an OR circuit with the second output of the analysis system and the second output of the control circuit with the third Output of the analysis system.

The function of the known computer processor exists in that the operands with their signs are first stored in the registers of the first and second operands.

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The information about the sign of the operands is passed to the analysis system.

After an instruction for the operation to be performed, any rational operation - multiplication, addition and subtraction - can be, the module arithmetic unit determines the result, which is stored in the result register while the analysis system determines the sign of the result, which of its second output is also stored in the sign position of the result register. On command from the third output of the analysis system the result is put on the result track via the result output circuit.

The main disadvantage of the cited processor is the lack of units that perform the multiplication operations and division of arbitrary numbers.

In addition, the analysis circuit in the analysis system limits the processing of information takes place exactly in steps (conversion to zero), essentially the operating speed of such processors.

In order to understand the terms used in describing the present invention, the remainder class system is presented below briefly described.

In the remainder class system, the decimal number A is represented by the totality of the remainders that result from dividing the decimal number by each of the relatively prime numbers p ,, p ~, .... If OC ₁ denotes the remainder that results from dividing the decimal number A by p ^ at i = 1, 2 ... η, then the number A can be represented in the system of remainders

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put as

A = (Ot ₁ 06 ₂ , ..., OL _n ) (1)

The relatively prime numbers P ₁ , p ₂ ... ρ are called the base numbers of the residual class system.

The number P equal to the product of all the base numbers of the residual class system is called the range of the number system

P = P ₁ * P ₂ '...' P _n (2).

Suppose, for example, a residual class system, consisting of three base numbers, d. H. η = j5> given:

P ₁ = 7, P ₂ = 9, P ^ = 11.

Then the range P of the number system is the same: ρ = 7. 9. _{n =}

One of the criteria for choosing the base numbers is that their product is greater than the maximum at one of the Operations addition, subtraction, division, multiplication, shift number involved.

Consider a decimal number A = 128 in the remainder class system. Dividing A = 128 by each base number results in the remainders te = 2, oCp = 2, oL-, - 7.

Thus, the decimal number A = 128 can be represented in the remainder class system as follows:

A = (2, 2, 7).

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It should be noted that the area P of the number system characterizes that set of numbers that are unambiguously can represent in the residual class system.

In the example shown, the range of change for the numbers clearly shown in the residual class system is within the interval (0.693). The maximum in the residual class system The number that can be represented is 692, since every number from the number range from 0 to 692 is the only remainder corresponds, while for example the number 26 and the number 719 in the remaining class system under consideration have the same type of representation:

26 = (5, 8, 4)
719 = (5, 8, 4).

The determination of the remainder when dividing the number A by the base number p- ^ of the number system is referred to as;

A = <& mod pi '(3).

The residual class system considered here is most suitable for performing rational operations (module operations) that are executed during a micro clock of the computer. This is usually used for the machine implementation of rational operations uses table arithmetic.

For example, let two operands A and B be given in the remainder class system

A = (Oc ₁ , Od ₂ ..., 06 _n ) and B = (^ ₁ , ß ₂ ... β _n )

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A = CX- ^ mod ^ ₁ and B = B = A ₁ mod P ₁ for i = 1,2, ... n,

Then the result S of any rational operation (addition, subtraction, multiplication) with the operands A and B as follows:

S -A * B-

ΐι- Vi * ßi ^raod

for i = 1,2, ..., n,

while the sign * - one of the operations of addition, subtraction or multiplication.

The division of whole numbers without a remainder can also be added to the rational operations:

with V. = ■ ■ mod ρ.
Di O ₁ i

for i = 1, 2, ..., n.

As an example, in the residual class system with the base numbers p. = 7, P ₂ = 9i Px = 11 the following rational operations with the operands A and B can be performed.

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1. Add A = 264 = (5, 3, O) and B = 377 = (6, 8, 3)

^ ₁ = 5 + 6 = 4 mod = 3 + 3 = 2 mod = 0 + 3 = = mod

So S = (4, 2, 3) = 64l.

2. Form the difference between the operands A = 591 = (3, 6, 8) and B = 201 = (5, 3, 3)

= 3 - 5 = -2 = 5 mod 7 = 6 - 3 = 3 mod 9 = 8 - 3 = 5 mod 11

So S = (5, 3, 5) = 390.

3. Form the product of the operands A = 23 = (2, 5,1) and B = 25 = (4, 7, 3)

X ₁ = 2, 4-8 = 1 mod f ₂ = 5, 7 - 35 = 8 mod = ι, 3 = 3 mod 11

So S = (1, 8, 3) = 575.

4. Form the quotient by dividing the operand A = 520 = (2, 7, 3) by B = 40 = (5, 4, 7)

7 = 6 mod

^{2 = 4 mod}

? r- = = 2 mod

So S = (6, 4, 2) = 13.

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The formation of the difference S between the operands A and B can be represented by the following equation:

SAB- (JT ₁ , Jf ₂ , · .., If ₂ ) (6)

where y. = oO. - (b ^ mod p ^ at i = 1, 2, ... η is.

To reduce the amount of processor equipment to be used When performing the addition and subtraction operations, the subtraction operation should be performed by the following operations be replaced.

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I »Operand B by its complement! B? - except for the P area replace, i.e.

B ¹ = P - B (7)

or in the He stklassensyste m

B "= (f _v J> ₂ , ...... J> _n ) (8th)

where ß ' = p £ - p £ mod p at ι = 1, 2,. ·. ·, η is

Determine II · 3a suit at S "by adding the operand A with the operand B *:

β-; ι * Β · 'Ij],} fi · fi> C9)

Jf i «rf £ + (P £ - ^ J) =« * i - ^ * _χ »Od p £

at ι = 1 | 2, ..., η is *

Thus, S a S ".

For example, in the reet class system with the base numbers p ^ r 7, p ₂ 3 9 »P3 = 11 the operation subtraction with the operands A and B is carried out«

The difference between A s 573 = (6, 6, 1) and E = IO3 a (5t 4. 4) is displayed * ·

I. Calculation of the complement B * of the subtrahend B up to the range P. Ss results
6 _Λ = 7 - 5 = 2 mod 7

- 9 - 4 ". 5 ^mod 9
= 11 - 4 = 7 mod 11.
Then ß »a (2, 5» 9).

II Calculation of the difference S. The result is:

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= 6 + 2 a 1 mod 7
s 6 + 5 = 2 mod 9

, s 1 + 7 β 8 mod 11.
Thus 1st S = (1, 2, 10) = 4-7Ο.

From what has been said above goes out; shows that the rational operations (module periods) are carried out simultaneously and in parallel for each of the base numbers P ₁ , Ρ ₂ ι ··· ι P _n ^ e ³ number system rational. Operation participating operands, as is the case in the position system. In addition, table arithmetic is used for the machine implementation of the rational operations, which makes it possible to exclude the transfer circuits in the corresponding adders when performing rational operations (module operations). This offers the possibility of adding two operands represented in the rest class system during a micro-cycle of the computer, which is only possible theoretically with the poaltion systems (basic writing catfish).

The result of the national operations (module operations) Addition, subtraction, multiplication are correct if the ■ Vert of the operands participating in the operation and the value det Results belong to the interval (O, P), i.e. smaller than the ! Area P of the number system are.

When adding two positive operands Λ and B in the remainder class system, a situation is possible where the received

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-IX-

Result greater than the range P of the number system, i.e.

A + B> P.

It becomes, for Baispigl _f in the residual class system with the base numbers p, - ss 7, Pp = 9t Px ^s H, the addition of the operands A a 264 s (5, 3, O) and B a 56I s (1, 5,0) carried out.

s 5 + 1 + 6 mod 7
s3 + 3s6 mod 9
= 0 + 0 = 0 mod 11
So ö = (6, 6, Ö) = 182,

In reality, A + B β is 264 + 561 = 82% This phenomenon is called overflow · The signal the presence or absence of an overflow is indicated in of the present invention denoted by X and overflowing ic] called «Here is

I if there is an overflow »if there is no overflow.

To determine the value of the overflow. »Character JL boi algebraic addition of operands A and B, each operand must be accompanied by its sign · The corresponding operation addition or · subtraction is also implemented taking into account the signs of operands A ₉ B»

In the present invention, Z is the information denoted by the sign of the operand A, B, while dar lower index of Z corresponds to the operand-. to which this Character relates · In particular, the sign of the operand

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A with Ζ., The "sign the operand B with Z ,,, the sign the result of the algebraic addition of the operands A and B labeled with ώ ^

For more convenient arbelt bits the operands are signed in the present invention the following values 2 ^ of the operand <A accepted;

0 if the sign of A is positive,

1, if the sign of A is negative , 5, 10) formed:
V ₁ s 1.6 a 6 mod 7
Y _{2 s} 1.5. = 5 mod 9
^ ₅ = 5.1O = 3O = 6 mod 11
Jbomit is S s (6, 5, 6) ss 545.
In reality the result is S = AB = 379.23O = 8717O

This resulted in the rational operation being carried out (Module operation) multiplication a wrong result, be there Value greater than the range P = 693 of the number representation in Restclass.system is »

Therefore, the multiplication must be more arbitrary in the rust class system The task of determining the operands shown of the multiplication result can be drawn without having to

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what limits on the size of the superanden and the size of the Result, except that they are used for the Range P of the number system belong

The term result S ¹ becomes the abbreviated multiplication according to the rule

S »s A · B / P (10)

introduced.

The determination of the result S ^{1 of} the abbreviated multiplication is the main operation when multiplying the operands in the remainder class system

In the example under consideration, the result S * results from the abbreviated multiplication of the operands A a 379 and B = 2 ^ 0

S ^! = 87170 a 125

It is now clear that if the result of the multiplication of the operands A and B is smaller than the range P, then the result S ^{1 of} the abbreviated multiplication is also WuIl, that is, S ¹ = O,

In addition, in the machine display, the choices m are usually represented by real fractions. For the residual class system, the range P of the number system is usually used as the denominator. In this case the following operands result: A ¹ = A / P, B 's B / P (11)

Then the result of the multiplication of the operands ü ^! and express ^{B 1}

A ¹ - B ' _s A / PB / P = A. B = J3 (12)

p2. P.

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where ΰ ¹ s A · B / P.

Thus, the multiplication of fractions in the rust classification system is also traced back to the determination of the result S ^{1 of} the abbreviated multiplication of the counters of the operands A ¹ and B '»

When dividing arbitrary ones in the remainder class system similar difficulties arise in the determination of the result.

The result S is to be determined by dividing the operand A s (5, 7, 10) s 439 by the operand Ba (2, 5, 9) = 86. The result is obtained by applying the rational operation Divisxon from A cbiüch B.

It surrenders

5 + 7. = 6 mod 7

= JZ = 7 + 2.q a 5 mod 9

5 .5

= 1 ° = 10 + 4.11 = 6 mod 11

9 9.

So S = (6, 5>, 6) =

In wiukliohkeiti the result is S

S = A = 439 s, - 9 B "86 ^ 86

The rational operation (module operation) division gives a wrong result, since the operand A cannot be divided by the operand B without a remainder.

"That's why you have to divide arbitrary in the rest class system represented the whole ϊβΐΐ the result

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to determine tates without any restrictions on the value of the operand A, which counts as a dividend, can be introduced «.

It is known that to carry out the operations Multiplication, division, determination of the overriding sign Knowledge of the rest of the operands participating in the operation The information via the value of the number in the position system, for example in the decimal system! which is given as a rank (see I, J. Akuschsky, D.I · Inditsklj, machine arithmetic in remainder classes. Ivioskau, "Sowjetskoje Radio", 1968) or transition to the number system with mixed Base numbers (see »Szabo N.S., Tanaka R.I», Restside Aritmetic and its Applications to Computer technology, Mc ürow-Hill, New York (1967)) required

Operations to be carried out information about the value which is needed in the position system is called tolohtmoduleoporations These operations include, in addition to the multiplication of fractions and whole numbers, the division of whole numbers, the determination of the overflow, -sign also the division of BrÜchenj division by the base number of the number system and the like.

In the present invention, the position £ 3 character _: R denotes the information about the value of the number in the position system

The index of the position character R corresponds to the number

to which this character belongs _t and "Ziwar becomes the position character of the operand A" with R * and the position character of the operand

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denotes the B with FL _1.

The invention is based on the object of creating a computer processor that allows the operations Realize multiplication, division and shifting of arbitrary numbers represented in the residual class system.

This is a task for a

^{Computer processor for 1} numbers represented in the residual class system,

with registers of a first and a second operand, the input of which is connected to an input rail of the first or second operand is connected,

with a module arithmetic unit to carry out the operations: multiplication, subtraction and addition within the Number system area, whose first and second input to the output of the register of the first and the second respectively Operands and their third input are connected to a control rail,

with a first and a second sign register for the sign of the first and second operands, the Input is connected to a first or a second input sign rail,

with an analysis system to determine the sign of the result and the overflow sign, from which are connected: a first and a second input to the output of the Register of the first or second operand, a third and a fourth input with the output of the first or second sign register and a fifth input with the control rail and an output with a fourth input of the module arithmetic unit,

with a result register for the result of the operations carried out, of which a first input with a

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sixth input of the analysis system is combined and connected to the output of the module arithmetic unit, while the output is connected to a result output rail, and

with a result sign register for the result sign, the input of which is connected to a second output of the Analysis system and whose output is connected to a result sign output rail, solved

by a first and a second position symbol generator for calculating the position symbols of the first and second operands, the input of which is connected to the output of the register of the first or second Operands and the output of which is connected to a seventh or eighth input of the analysis system;

by a multiplier ^
by a divider and

by a shift device for shifting an operand,

whose first entrance is united and sent to the

Control rail j, whose second input combined and to the output of the second position symbol generator and its third input is also combined and connected to the output of the register of the second operand,

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also the fourth input of the multiplier and the divider combined and combined to the output of the register of the first operand and the fifth input of the multiplier and the divider and connected to the output of the first position symbol generator, while the output of the multiplier ^ of the divider and the first exit of the sliding device ^! 'with a second ·. or third or fourth '' ^ input of the result register and the second output of the shifter with a ninth input. ■ the analysis system are connected, and

by an overflow character register for receiving the overflow character when adding and subtracting the first and second operands, whose input with a third output of the analysis system and whose output with an overflow character output rail 'is connected.

It is appropriate
that the analysis system has:

an operation decoder for converting the control signal into an operation corresponding to the operation to be carried out Binary code whose input 'is connected to a fifth input of the analysis system "·,

eleven AND circuits

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where the first input of the first, second, third,, fourth, fifth, sixth, seventh and eighth AND circuit combined and to a first output of the operation decoder are connected

the second input of the same AND circuits and the second input of the eleventh AND circuit · with the fifth bz / ί third or fourth or first or seventh or second or eighth or sixth or ninth input of the analysis system is connected,

the first input of the ninth AND circuit with a second output of the operation decoder, "and the the second and third input are connected to a third or fourth input of the anylsis system (18),

of the tenth AND circuit, the first input is connected to the fourth input of the analysis system is, and the second input is combined with the first input of the eleventh AND circuit and to a third The output of the operation decoder is connected,

an analysis device for determining the sign of the result and the overflow character when adding and subtracting the first and second operands,

a first OR circuit and a second OR circuit

a modulo-2 adder to generate the result sign in multiplication and division,

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whose first and second input are connected to the first and second output of the ninth AND circuit, respectively are,

the first and second inputs of the first OR circuit with the output of the modulo-2 adder or the tenth AND circuit and the output with the second output of the analysis system. are connected, the first input of the second OR circuit is connected to the output of the eleventh AND circuit ^s and the output is connected to the third output of the analysis system,

the third input of the first OR circuit and the second OR circuit '. with the third or fourth Output of the analysis device are connected,

whose first, second and fifth output are combined and connected to the first output of the analysis system, while the inputs "'with the output of the first, second, and third and fourth and fifth and sixth, respectively. or seventh or eighth ■ AND circuit are connected.

The present invention makes it possible to create a principally new family of computers, which in the rest working class system.

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As the circuit-wise solution of the professor on the union of individual assemblies, each of which. sme operation executes independently of the other assemblies, - this allows the necessary structure of the processor starting to choose from then the concrete requirements of the oenutaers

In addition, the work of the Reohners > in the Hest class system, which allows the use of the channel structure for the processor gastati / et (for each:, - basis of the number system), increases its working speed and reliability.

The invention is illustrated below using an exemplary embodiment

explained on the basis of the attached drawings. Show it"

Block diagram,. V

E ¹ Ig _n 1 cfän ■ / of the processor according to the invention}

"circuit diagram
2 shows the block of the analysis system according to the invention

The processor for numbers represented in the hest class system contains registers 1, 2 (Flg. 1) of the first and second Opei'anden

The input 3 of register 1 and the input 4 of the Regl ^ v · -: stars 2 are each connected to the input rails 5i 6 & ® ^Ώ first and second operands ·

The processor also has a «module» Kechen-werk. 7 on,

whose first input 8 and second input 9 a * i <lie outputs of the Eiegister 1,2 of the first and second operands connected sixkI, while its third input 10 is connected to the control rail 11 is·

The processor also contains one: first sign register

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- 2Ö-

12 and θ in; . second Vo i soft nil eg is ei 13o The input 14 of the Register 12 and the input 15 of register 13 are respectively to the first and second Yorzeichansohiene 16 and 17 connected

The processor also includes an analysis system 181, the first of which Input 19 and second input 20 each with the outputs the registers 1 and 2 of the first and second operands are connected, while the third input 21 and the fourth input 22 to the outputs of the first sign register 12 and the second Sign register 13 are connected, the fifth input 23 is in communication with the control rail 11, with an output connected to the fourth input 24 · of the module arithmetic unit · 7

The processor also has a results register 25, whose first input 26 out the sixth input of the analysis system 18 combined and with the output of the module arithmetic unit -

7 is connected, while the result register 25 is connected to the result output line 28 connected

The processor contains an * ·. Result sub-digit register 29, its input 3 ^ to the second output of the analysis system 18 is connected, while its output is connected to the sign output «· rail 31 is connected ».

The processor also has a first generator32 and a second generator 33 on.

Dar input 34 of the generatorfe 32 and the input 35 of the generator 33 are each connected to the outputs of registers 1 and 2 of the

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or stan and second operands connected while the output each Generat as 32 and 33 respectively to the seventh input 36 "and the eighth input 37 of the analysis system 18 are connected

Dar processor includes a he multiplier 38, emenDividierer 39, a shifter whose 4O ₁

first inputs 41, 42, 43 combined and to the control rail 11 _9, the second inputs 44, 45, 46 also combined and to the output of the second generator 33, the third inputs 47, 48, 49 and to the output of the register 2 of the second operands, fourth inputs 50, 51f of multiplier 38 and des

Divider 39 combined and to the output of the da β register 1 of the first operand, the fifth inputs 52, 53 of the multiply rs 38 and the divider 39 combined and are connected to the output of the first generator 32

The outputs of the multiply 38 and dos dividie

rers 39 and the first output of the sliding device 40

are each connected to the second input 54 »äem third input ^ 3 and the fourth input 56 of the result register 25 ·

The second output of the sliding device 40 is with the ninth input 57 connected to the analysis system 18

The processor also contains an overflow character register 58, the input of which is connected to the third output of the analysis system 18 and the output to the overflow cell output rail 60 are·

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According to the invention, the analysis system 19 contains an opera * tion decoder 61 (Fig. 2), its input 62 with the fifth Input 23 of the analysis system 18 connected 1st, and also eleven AND circuits 63, 64, 55, 66, 67, 68, 69, 70, 71, 72, 73.

The first inputs of the first 63, second 64, third 65, fourth 66, fifth 67, sixth 68, seventh 69 and eighth 70 AND circuits are combined and connected to the first output of the operation decoder 61, while the second inputs of the same AND Circuits 63-73 and the second input of the eleventh AND circuit 7 ^ are each connected to the fifth 23, third 21, fourth 22, first 19, seventh 36, second 20, eighth 37i, sixth 27 and ninth 57 inputs of analysis system 18.

The first input of the ninth AND circuit 71 is connected to the second output of the operation decoder 61, while the second and third inputs are connected to the third 21 and fourth 22 inputs of the analysis system 18, respectively.

The first input of the AND circuit 72 is connected to the fourth input 22 of the analysis system, while the second input is combined with the first input of the eleventh AND circuit 73 and connected to the third output of the operation decoder 61.

The analysis system 18 also has an analysis device 74, a first 75 and a second 76 AND circuit and a modulo-2 adder 77.

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The first and second inputs of the modulo-2 adder are each with the first and second output of the ninth AND circuit 71 connected.

The first and second inputs of the IMD circuit 75 are each with don outputs :! of the modulo-2 addiexer and ten-tone AND circuit connected while the output to the second output of the analysis system 18 is connected.

The first input of the second OR circuit 76 is connected to the output of the eleventh AND circuit 73 , while the output to the third output of the analysis system 18 is analyzed.

The first input 78 _for the second input 79 »dQ £ third input 80, the fourth input 81, the fifth input 82, the sixth input 83 'of the seventh input 84 · and the eighth input 85 of the Analyseneinriohtung 74 are respectively connected to the outputs of the first AND circuit 63, second AND circuit 64, third AND circuit 65, fourth AND circuit 66, fifth AND circuit 67, sixth AND circuit 68, seventh AND circuit 69, and eighth AND so holding 7O connected. Dar first, second and fifth exit; of the analysis device 74 and connected to the first output of the analysis system 18, while the third output is connected to the third input of the first OR circuit 75 and the fourth output to the second input of the second OR circuit 76 «

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The processor according to the invention works as follows »

The first operand A from input rail 5 (FIG. 1) of the first operand and the second operand B from input rail 6 of the second operand are received by registers 1 and 2 of the first and second operands, respectively. At the same time, the sign Z. of the first operand A from the input sign rail 16 and the sign Z i of the second O £> eiranden B from the input sign rail 17 are each stored in the first 12 and second 13 sign registers. In addition, the first operand A and the second operand B arrive from the outputs of the registers 1 and 2 of the first and second operands to the inputs 34 and, respectively. 35 of the first 32 and second genera.tas | b.er position characters R. and R _{B of} the first and second operands »

The processor continues to work as a function of the steaif signal given on the control rail 11

If the control signal taken from the control rail 11 corresponds to the operation multiplication of arbitrary numbers or fractions, this is how the multiplier 38 works

to their fourth input 3O and third input 47 from the outputs of registers 1 and 2 of the first and second operands given the first operand A and the second operand B while on the fifth input 52 and the second input 44 from the outputs of the first generator 32 and the second generator 33 the position symbol R, the first operand A and the position symbol R "of the second operand B can be given. The result of the ope—

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ration Multiplication is based on multiplying 28 saved in your results register 25

To determine the result before ^{3 of} the multiplication operation, the signs Z ^ and Z _{33 of} the first operand A and the second operand / B are transferred from the outputs of the first sign register 12 and the second sign register 13 to the third input 21 and the fourth input 22 of the analysis system 18 given. Here, the control signal passes from the control rail 11 via the fifth input 23 of the Analysensyutems 18 to the input of Operationsdecodierers 61 (Fig x 2) · In this' case, the signal passes _f the giei eh ^One:> is, from the second output of the Operationsdecodierers 61 The signs Z. and Zg of the first operand A and the L-white operand B are given to the first input of the named UliD * circuit 711 at its second and third input The signs Z ^ and Zn of the first operand A and the second operand B reach the input of the modulo-2-addition77. At the output of the addleret77 the sign Zg of the result S dejc operation multiplication is formed, which is given via the first OR circuit 73 to the second output of the analysis system Formula to be illustrated »

where the sign (+) represents the addition operation with respect to the

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i'uoduls two bo da practice »

The sign Z _e for the result of the operation toultipllkution arrives from the second output of the analysis system 18 to the register 29 for the sign of the result and is stored in it. The operation multiplication of the arbitrary operands A and B is thus ended, the result S of the operation multiplication and the result svwU sign Z _g are stored in the result register 25 (I ¹ Ig. 1) and in the result register 29.

If the control signal from the control rail 11 corresponds to the division of arbitrary numbers operation, the operates

Divider 59 · Here, the first operand A and the second operand B are given to their fourth input 51 and third input 48 from the outputs of the itogister 1 and the first and second operands, while the fifth input 53 and the second input 45 from the Outputs of the first generator and the second generator $ 3 of the position ze conduct R. and Sp of the first operand Λ and the second operand B are given. The result of the operation division is brought into the result register 25 from the output of the divider 39.

The 'determination of ^ q ₃ sign Z _ß for the result S of the operation division is similar to the determination of the result sign of the operation multiplication »

The result S of the division operation and the sign

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! ώ _ο füi the guarantee are saved in uam jiiejdD.alsrugister 25 and the urge bnisvor sign reg ister 29. The formation of the Uüai 'sign JL is not necessary in the case of operations that are described as being dQi', since both the superands A and B as well as the result S represent the OpyNations division and iuuitip ± i-Jtation within the range P. des ^ ahlensysiems iiogen.

üntspiioht the Stöuersi ^ naX of dex ütaueischiene 11 & q £ Upuiatlün VQJc shift (by one üit), so the Jchiobe-

Φ * üiejCDüi is given on its second Ειη ^ αη ^ 4-9 from the ßagisiiers 2 of the second Opeuandan dojc second upauand B and on its two Ein ^ ans 46 the position rich Bg of the üwuition operand B from the output of the second generator 33 üirgeonis aur Vorschiobung is brought from the first output of the sliding device 40 to the result register 25.

Since the sign 2 ^ for the result of the Vei'ochiaDung with your prefix £ 'of the operand B to be shifted coincides so in this fc'alle with a control signal from the Rail 11 at the third output of the operations decoder s 61 (.big. 2) generates a signal that corresponds to, one. The sign

L · of the second operand Jd arrives via the fourth passage 22 of the analysis system 18, via the tenth UÜD circuit 72 and the first OUÜR circuit 75 ^ to the second output of the analysis system 10. The sign of the result S of the combination of the second operand B is entered into the result sign register 29 from the second output of aes üaalyse systems 18 (! «Ig · 1).

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Memory to

The displacement of the second operand ü Xn dur üchiebeeini ^T ich1iung 40 may be improved by Rechta carried out and to the left (to EXN JBiT) · üxerbei Can Del left shift EXN result S obtained aas aen area P of the number system · exceeds In this i'ulle is at zwexten output of means 40 is a üignal corresponds to the Exns generated and gegeoen to ninth input 37 cless analysis system _e From the ninth commonly 57 (-fe'ig x 2) of the analysis system 18 passes this signal on the eleventh aND Circuit '/ 3 and the second OÜBK circuit 76 to the third output of the analysis system and is stored in the ÜDerlaufszeichenregister 58 (iJ'lg. Ό.

This concludes the shifting of the second operand B, the result ΰ of the spanking manure and the individual Z “of the result are stored in the result register 25 and a result presentation register 29 58 stored, wöbe χ its contents' Sxne

corresponds if there is a ÜDeriaui when shifting to the left, and .zero when moving to the left and no overflow to the right xst

If the control signal from the control rate 11 corresponds to an algebraic addition of the operands A and B _f, then the module arithmetic unit operates

8 and two from connection 9 from the outputs of registers 1 and 2 of the first and second operands are the first uporand A, the second

609841/0907

Operand B given · The result S, that of the algebraic sum (without taking the sign into account) of the first operand A and of the second oporand B is the same, is determined by the output of the unit 7 given to the sixth Elngaiog 27 of the analysis system

With a control signal from the control rail 11, the Ubei the fifth passage 23 of the analysis system 18 on the passage of the regeneration decoder 61 (i'lg * 2) appears at its first output a signal that corresponds to Bins «

The first Uporana A and the second operand B come from the first input 19 Ci ¹ Ig * 1) and the second input 20, the position _{symbols B. and R £} from the seventh input 36 and eighth input 37, the sign Z. ' and £ “of the first superand A and aes second operand B from the third input 21 and fourth input 22, the result S from the sixth handling of the analysis system via the fourth 6b (2), second 66, ι unite 67, seventh 69 , second 64, third 65 and-MUHiAe 7 ° AND circuits to the inputs of the analysis device 7 ^ ·

The third and fourth exit, you & analysis direction 74 become control signals for forming complements to the range P taken from the number system of the first A and second B operands The fifth output of the analysis device 74 is a Control signal for the formation of a complement to the area P des 'kianiensystem of the result of the arithmetic sum of the first A and the second B operand taken from the control signals from third, fourth and fifth output 'of the analysis device

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74 get over the first output of the analysis system for the fourth input 24 (i'lg x 1) of the module calculating unit 7 · I ¹ jach the jjurchfünrung the eriordeiliehen operations, which are caused by this signal is the output of the module -Rechenwerks 7, the Result S of the algebraic addition of the first A and the second JB operand taken, which is in aem cone 25. is saved

item becomes the first output of the analyzer 74 (FIG. 2) the sign Zg cLös result S of the algebraic «addition taken, which about the first 012BB-Sohaltung 75 and the second Output of the analysis system 18 in the result sign register 29 Oä'ig is saved

The overxauf ^ zelohen JC is taken from the second output of the analysis device 74 (üig · 2) , which 'does the second OIÜR circuit 76 and the third output of the analysis system is stored in the overla ui_ze lohenreg ister 58 C-b'ig · D will·

Thus, the simultaneous work of the wodui arithmetic unit 7 and the analysis system 18 forms the result of the algebraic sum of the first A and second b operands, the sign Zq of the β result S and the overflow soft JL '.

uie each m AEM urgebmsregister 2j ?, AEM argyünisvorzeichenrägister .29 and the ÜDeriaui_Zöichenregister 58 ge spei before ⁵ * · In the case aer i / rational upuxationen (Moduioperaiiionen) urchflinrung multiplication and division innärnttib de * region P

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the number system works · the module arithmetic unit. Here- · bai are on their first input 8 and second input 9 from the outputs of registers 1 and 2 of the first and second operands the first operand A and the 25th operand B given · The Result S of the performed rational operation becomes the output desReciBnweris 7 fl & the result roster 25 brought

The determination of the sign "; 2g of the result S the rational operation is carried out with the help of the analysonsystom 18 similar to the operations considered multiplication and Division, where the sign in the result sign-ugister 29 is saved

iJaturlioh needs rational operations to perform the overflow ^ character JL will not be calculated in bold, since both the value of the first operand A and the second operand B as well as the value of the result S does not exceed the range P.

The invention enables "the construction of a principle

new class of computers _ that work in the residual class system «

The inventive processor ensures multiplication and division of arbitrary ones represented in the remainder class system Numbers without extension of the range P the output number system, the determination of the overflow symbol, the determination the sign of the result for any operation that does Zahlonversohle practice near right and left as well as the execution any rational operation (module operation) within of the area P of the number system «

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It also allows the creation of a residual class system working processor, diQ working speed and to increase the reliability of the Hechners

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Claims (2)

Claims Γΐ J computer processor for numbers represented in the residual class system , with registers of a first and a second operand, the input of which is connected to an input rail of the first or second operand is connected, with a module arithmetic unit to carry out the operations: Multiplication, subtraction and addition within the number system range, its first and second input to the output of the register of the first or the second operand and its third input to a control rail are connected with a first and a second sign register for the sign of the first and second operands, the Input is connected to a first or a second input sign rail, with an analysis system to determine the sign of the result and the overflow sign, from which are connected: a first and a second input with the output of the register of the first or second operand, a third and a fourth input with the output of the first or second sign register and a fifth input with the control rail and an output with a fourth input of the module arithmetic unit, with a result register for the result of the operations carried out, of which a first input with a 609841/0907 - 3β - sixth input of the analysis system is combined and connected to the output of the module arithmetic unit, while the output is connected to a result output rail, and with a result sign register for the result sign, the input of which is connected to a second output of the Analyzer system and its output is connected to a result sign output rail, marked by a first (32) and a second (33) position symbol generator for calculating the position characters of the first or second operand, whose input (34, 35) with the output of the register of the first (1) or second (2) operand and its output with a seventh (36) or eighth (37) input of the analysis system (l8) is connected; by a multiplier (38),
by a divider (39) and by a shifting device (40) for shifting an operand, its first input (4l _s 42, 43) combined and to the control rail (11), its second input (44, 45, 46) combined and to the output of the second position symbol generator (33) and its third input (47, 48 , 49) is also combined and connected to the output of the register (2) of the second / second operand, 609841/0907 furthermore the fourth input (50, 51) of the multiplier (38) and of the divider (39) combined and to the output of the register (l) of the first operand and the fifth input (52, 53) of the multiplier (38) and the divider (39) combined and connected to the output of the first position symbol generator (32), while the output the multiplier (38), the divider (39) and the first output of the shifter (40) with a second (54) or third (55) or fourth (56) input of the result register (25) and the second output of the shifting device (4o) are connected to a ninth input (57) of the analysis system (18), and through an overflow register (58) for receiving the Overflow character when adding and subtracting the first and second operands, whose input (59) with a third The output of the analysis system (18) and the output of which is connected to an overflow signal output rail (60) (Pig. I). 2. Computer processor according to claim 1, d. a characterized by that the analysis system (l8) has: an operation decoder (6l) for converting the control signal into an operation corresponding to the operation to be carried out Binary code whose input (62) is connected to a fifth input (23) of the analysis system (l8), eleven AND circuits (63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73), 609841/0907 the first input of the first (6j5), second (64), third (65), fourth (66), fifth (67), sixth (68), seventh (69) and eighth (70) AND circuit combined and are connected to a first output of the operation decoder (6l), the second input of the same AND circuits (63-70) and the second input of the eleventh AND circuit (73) with the fifth (23) or third (21) or fourth (22) or first (19) or seventh (36) or second (20) or eighth (37) or sixth (27) or ninth (57) input of the analysis system (18) is connected, the first input of the ninth AND circuit (71) with a second output of the operational decoding chip (6l) and the second and third input are connected to a third (21) and fourth (22) input of the anylsis system (l8), of the tenth AND circuit (72) the first input with the fourth input (22) of the analysis system (18) is connected, and the second input is connected to the first input of the eleventh AND circuit (73) combined and connected to a third The output of the operation decoder (6l) is connected, an analysis device (7 ^) for determining the sign of the result and the overflow character when adding and subtracting the first and second operands, a first OR circuit (75) and a second OR circuit (76), a modulo-2 adder (77) for generating the result sign in multiplication and division, 609841/0907 whose first and second input are connected to the first and second output of the ninth AND circuit (71), respectively are, the first and second inputs of the first OR circuit (75) being connected to the output of the modulo-2 adder (77) or the tenth AND circuit (72) and the output are connected to the second output of the analysis system (18), of the second OR circuit (76) the first input to the output of the eleventh AND circuit (75) and the output are connected to the third output of the analysis system (l8), the third input of the first OR circuit (75) and the second OR circuit (76) with the third and fourth, respectively Output of the analysis device (74) are connected, whose first, second and fifth output are combined and connected to the first output of the analysis system, while the inputs (78, 79, 80, 81, 82, 83, 84, 85) with the Output of the first (63) or second (64) or third (65) or fourth (66) or fifth (67) or sixth (68) or seventh (69) and eighth (70) AND circuit are connected. $ 09841/0907