DE2712582C2 - DDA computer (digital differential analyzer) - Google Patents

Description

The invention relates to a DDA computer (digital differential analyzer) according to the preamble of Claim.

Digital differential analyzers or integration systems or differential equation machines (hereinafter referred to as as DD A's) are used for the solution (integration) of differential equations and work according to the Principle of calculating the area of a segment area.

The DDAs can be used in series DDAs in which a digital integrator carries out operations in series, and divided into parallel DDAs in which all digital integrators work at the same time.

Series DDAs are less complex, since an arithmetic unit including the integrator is used together can be. The result is accurate because that's zuvo? found a result of the integrator on the following Operations can be recovered. For this reason, serial DDAs have mostly been used up to now. These works but slowly, as the digital integrator steps through the operations.

On the other hand, parallel DDAs work very quickly because all digital integrators are used at the same time. However, since the input signals (primary increment and secondary increment) of the digital integrator are always on those of one or more previous iteration times are limited, depend on the degree of delay these input signals require various compensation operations. Since the compensation operation becomes complicated, the arithmetic units required also become complicated. Hence can with parallel DDA's, which require an arithmetic unit for each digital integrator, is difficult to enter DDA suitable for practice can be achieved if the arithmetic units are not built with fewer components and the operations are carried out quickly.

As with a conventional digital calculator, the operations in the DDA can be divided into three categories will:

Series addition, in which the data are added bit by bit,
Parallel addition, in which all bits are added at the same time, and
a combination of these.

The series DDA, in which the common arithmetic unit can be used, generally uses parallel addition, to achieve a high speed of operation or operation, during the Parullel DDA generally the series addition is used to reduce the number of components. However, since the parallel

■ mmatim

Addition is superior to serial addition in terms of operating speed, some use parallel DDAs the parallel addition to achieve the high operating speed. In the case of parallel addition, there is an alignment the bit positions of an integrated result and a secondary increment are required in order to do this to form a sum and this determines the operating time of the DDA.

Through the GB-PS 9 38 204 a DDA computer has become known in which a single, working in series Integrator in time division multiplex operation is used to carry out integration operations on data, which are delivered from a memory with random access. The retrieval of data from memory and the Results are written in using a stored program. In contrast to the present invention only one arithmetic operation can be carried out with this DDA computer; an overlapping one Operation of calculators is not possible.

A DDA computer working in series with several integrators is also known (Journal BriL I.R.E., May 1963, pp. 461-473), in which the increments for the integration variable are represented by a multi-digit binary number being represented. With this “increment computer”, the data intended for processing are assigned to the integrators delivered by delay lines. In contrast to the present invention, the "Increment calculator", however, does not change the operating mode, especially that for calculating the tertiary increment very firm.

The "pipelining concept" is also known in computer technology. H. the arrangement of buffers between individual, one behind the other arranged arithmetic units, so the possibility of to create simultaneous processing of data in the arithmetic units (IEEE Transactions on Computers, August 1972, pp. 880-886; "Taschenbuch der Informatik", Springer-Verlag, Berlin, Heidelberg, New York 1974, Pp. 170-175; Electronic computing systems, 1975, issue 2, p. 80-83), but this well-known concept does not apply Note how a known DDA-R;: computer must be designed in order to shorten the operation time while at the same time achieving optimal accuracy of the calculation result.

It is therefore the object of the present invention to provide a DDA computer according to the preamble of the patent claim with high operating speed and optimal calculation accuracy.

This problem is solved by the features specified in the characterizing part of the claim.

The invention is explained in more detail below with reference to the drawing. It shows

Fig. 1 is a circuit diagram of an embodiment of the DDA according to the invention,

Fig. 2 signals for explaining the operation of the circuit of Fig. 1,

3 to 7 specific exemplary embodiments of parts of the circuit of FIG. 1, namely one in FIG Voters, in Fi g. 4 a decoder, in FIG. 5 a primary increment discriminator, in FIG. 6 a tertiary increment decider and in Fig. 7 a J-K flip-flop, and

FIG. 8 is a table for explaining the relationship between the input / output of the decoder of FIG Fig. 4 and the mode of operation.

Before an embodiment of the invention is explained in more detail, its principle should first be described will.

The operating time of a digital integrator generally consists of a time 7> which is required to calculate the total sum of a secondary increment, a time T _s > which is required to align the bit positions when adding the secondary increment to an integrand , and a time 7) required to calculate the integral to generate a tertiary increment (including a time required to compensate). Although the invention is applicable to either parallel addition or series addition, significantly more advantages are achieved and fewer circuit components are required when it is used for series addition. Therefore, the series addition DDA is explained in more detail below.

In the case of serial addition DDA, Ts has the value zero, since the alignment of the bit positions when adding the secondary increment to the integrand can be replaced by setting the time for its addition. The operating time Γ of the digital integrator in the series addition DDA is thus given by:

where Tp depends on the type of addition for the secondary increments; if these are scanned one after the other for addition by a bidirectional counter, as will be explained in more detail below, 7> depends on the number of bits of the secondary increments; when these are added by an adder, Tp is determined by a data transmission delay time of the adder.

If, in conventional DDA, the adder for calculating the integrand, the adder for compensating and the adder for quantizing for calculating the tertiary increment are directly cascaded and all operations first for one bit of the data value representing the integrand and then the operations are executed for the next bit, the above time T ₁ depends on the data transmission delay time T _{d of} these adders and the number N of bits of the data value representing the integrand and is given by:

60 T ₁ = NT ₁₁ . (2)

If, on the other hand, in the invention buffer such. B. buffer registers are provided for temporarily storing the operation or operating results of the previous adders between the adders, the time T ₁ can be determined in the following manner. In particular, the data transmission delay time T, _m between the respective registers is given by:

Μ + \

(3)

with M - number of buffer registers between the adders.

Furthermore, in the case of the invention, the operations as a result of the buffer registers can be carried out simultaneously in the respective Arithmetic units are carried out. While z. B. the adder to compensate the compensation for a Bit, the adder for integrating can perform the integration for the next bit.

Accordingly, assuming that each adder performs the operation for one bit for each period (clock) corresponding to the data transfer delay time T _dB , M bit periods are required before the bit stored in the first stage buffer register is stored in the last stage buffer register will. Thus, (M + yV) -bit periods are required to perform the operations for the W bits. Therefore the time T _{1 is} given by:

, _e (4)

Accordingly, the operating time Γ of the integrator is given by:

_{r ll} (j) _u . (5)

With M> 1 it follows from equation (5):

(6)

Thus, the time T ₁ in the conventional DDA is given by the equation (2) and in the invention by the second term on the right-hand side of the equation (6). With N / bfSi 1, the operating time T ₁ in the invention is reduced by the factor / V / compared to conventional analyzers.
As explained above, the operating time 7 "can be reduced considerably if the buffer registers are provided between the adders. With, for example, 7> = 400 ns, N = 16, M = 4 and T ₁₁ = 400 ns, the Time T in the invention 2.0 i ^ s, which is more than 3 times shorter than in the case of the conventional arrangements with 7 = 6.8 iS.

Fig. 1 shows an embodiment of the DDA according to the invention. In Fig. 1, a selector 1 is provided for selecting signals + DYq, -DYo-, + DYi, + Z) J ^, -DY2 corresponding to the secondary increments dy and signals + DX, -DY corresponding to the primary increments dx at appropriate times, a bidirectional counter 2 for up or down counting of the secondary increments from the selector 1 in order to calculate the total sum of the secondary increments, a shift register 3 for adding the total sum of the secondary increments of the counter Z to an integral, Fiipfiops 28 and 29 for holding the primary increments, AND gates 6,7,8,10,25,33,36,38,42,43, OR gates 17,21,49 and inverters 9,35. In addition, adders 12, 1, 27, 39 are provided, the carry output signals of which are held in flip-flops 13, 18, 26, 40 in order to be used as carry input signals in the addition for the next bit. Furthermore, buffer registers 14, 15, 16, 22, 23, 31 are additionally provided in the invention as memory, which have flip-flops in the illustrated embodiment. Fiipfiops 45 and 46 hold the tertiary increment dz. Blocks shown with two boundary lines are D flip-flops. Furthermore, shift registers 11 and 41 are provided as first and eighth memories. The shift register U stores the integrand and the shift register 41 stores the remainder of the integral. They are referred to as K registers and Ä registers. Registers 4 and 34 are also provided. The register 4 stores a numerical value for designating the addition times of the secondary increment dy, and the register 34 stores a numerical value for designating the mode of operation. Although the contents of registers 4, 11 and 34 can be set externally, e.g. B. from a digital computer, it is assumed to simplify the illustration that predetermined numerical values were set in these registers prior to operation.

The content of the register 4 is given to a payer 5. When the content reaches the value zero, the counter 5 generates a borrow, which in turn sets a flip-flop 48. A decoder 37 generates a signal to determine the mode of operation; a tertiary increment decider 44 decides the presence or absence of the tertiary increment dz ', exclusive OR circles 24 and 32 calculate 2's complements and a primary increment discriminator 30 detects the positive, negative or zero value of the primary Increments dx. Furthermore, a switch 20 and a JK flip-flop 47 are provided, which indicates the polarity of the K register 11 (first memory).

Before the operation of the circuit of Fig. 1 is explained in more detail, the at various points in I described clock signals lying on the basis of FIG. The following example assumes that the number of bits of the y memory 11 or the λ memory 41 for storing the integrand or the remainder of the integral 16 is that the number of inputs at which the secondary increments are located has the value 3, and that there is an input to which the primary increment is output, although other numbers of the Bits of the registers and the inputs can be used.

In Fig. 2, 7 ″ (with η = integer) represents the times for controlling the operations of the registers, fiipfiops and counters in Fig. I, and DY denotes selection signals for the secondary increments corresponding to clock signals CT ₀ to CT ₂ , which are generated at times T ₀ to Ti , the selection signals being sent to the selector 1 to generate signals ± DY ₀ corresponding to the secondary increment dy ₀ at time T ₀ , signals ± DY \

corresponding to the secondary increment dy at time T, and signals ± DY ₂ corresponding to the secondary increment dy ₂ at time T ₂ . The clock pulse generated at the time 7 ,, CT ;, clears the flip-flops 13, 18,26 and 40, and the clock pulse generated at the time T ₂ CT ₂ reads the contents of the register 2 to the counter 5. The at time Tj, clock pulse generated CTT , is output to the selector 1 to select signals ± DX corresponding to the primary increment i / x. The clock pulse CTt also clears the buffer registers 14, 15, 16, 22 and 23 and sets carry-in signals to the flip-flops 26 and 40 upon subtraction. A pulse CYS generated during the time Ty gives the selected primary increment, the flip-flops 28 and 29 as the signals XA and XB lib UiV loads the total sum of the secondary increments added during the times T ₀ to T ₂ into the shift register of the input device 3. Clock pulses LCPzutn Setting of data in the buffer registers 15,18,22,23, 26 and 31 consist of 19 pulses which are generated at times 7j to T _{22, respectively.} YCP denotes shift pulses for the y register (first memory) 11 and also clock pulses for the counter 5 in order to determine the addition times of the total sum ^ dy of the secondary increments, and for the shift register of the input device 3 by the total sum l dy move. The pulses KCV are also set pulses for the puller registers 13, 14, 16 and 47 and have 16 _{pulses generated at times T 4} to 7Vj. ACP denotes shift pulses for the /? Register 41 (eighth memory) and also set pulses for flip-flop 40 and has 16 pulses which are generated at times T ₁ to T _22. CTi 9 represents a> | generated during time 7Vi

Pulse and serves as the J and «. Input signal of the JK flip-flop47. CT _n represents one during time -1

'Λ ι generated pulse and blocks an input signal from the fourth adder 39 to the Λ register 41, causes _; .J

a positive sign of the register 41 id. H. "O") and sets the output desTertii-r-lnkrcment-decision g

dcrs 44 to flipllops 45 and 46. 2u | j

Although the sections for generating these control signals are not shown in FIG. 1, $ j

the operation of the circuit of FIG. 1 on the assumption that the above control signals are sent to the appropriate |

th points in Fig. 1 lie. The embodiment of Fig. 1 is designed to use any of the following; |

can choose six values as the compensation term for the integration. In particular, if the compensation of f |

Λ 25 * "'

± ^ r ^ dy, for the integrated value> · ,, is executed, any of the six values -2, -1.0, + 1, +2 and +3 pjj can be used for K

to get voted. Furthermore, the exemplary embodiment is designed in such a way that a Hills operation and a comparison; $ |

in addition to integration. The auxiliary operation is as a create operation ||

of the tertiary increment, as shown in equation (7), depending on whether the content of / -register 11 is positive, j-

is negative or zero, and the comparison is defined as an operation to generate the tertiary increment as in 30 "itj

Eq. »; Hung (8), depending on whether the content of the K register 11 is positive, negative or zero, defi- Ji

nicrl: ^

(7) if

35; .i

(8) 4P

with

45

y, i = y, ι + ^ dy "

y, ι = operation result of the previous iteration, and

Σ '(ν, = circumferential total of the secondary increments.

50

In Fig. 1, the secondary increment signals + DY ₀ and -DY ₀ for the first bit in selector 1 are selected by the selection signal (clock pulse) CT ₀ , and the signals + DY \ and -DY, for the next bits are selected by the select signal CT \ and the signals Dy + ₂ and ~ DY ₂ for ^e 'n further bit are selected by CT. ₂ The primary increment signals + DX and -DX are selected by the clock signal CT ₃ .

The F i g. 3 shows a specific example of the selector 1 with an OR gate 51, gates or gates 52 to 54, inverters 55 to 57, AND gates 58 to 63 and gates 64 and 65 for generating a "1" signal. The remaining reference symbols correspond to the reference symbols of FIG. 1.

If the secondary increment signals + DY and -D ^ have the values (»1«, »0«), (»0«, »1«) or (»0«, »0«), the secondary- Increment dy +1, -1 or 0; with + DY ₀ = "1" and -DY ₀ = "0" the elements 52 corresponding to the connections Gi and Gg are opened by the clock pulse C7 "o, so that signals" 1 "and" 0 "at the connections G ₁₄ and G \ $ occur, which signals are output as upward and downward counting signals UP and DW to the bidirectional counter 2 in Fig. 1. In a similar way, the elements 52 corresponding to the connections G ₅ and G _{b are} through for the primary increment the clock pulse CTj is opened so that the signal DXS opens the AND gates 61 and 63 so that signals can be transmitted to the connections (J ₁₆ and Gn . At this point in time, the primary increment signals XA and XB at the connections Ci ₆ and Gn are generated, the primary increment for the flip-flops 28 and 29 in Fig. 1 being set by the clock pulse CTj The secondary increments Oy ₀ , dy _x and dy ₂ are added in counter 2 to give the total sum of the secondary The total sum ^ dy of the secondary increments calculated in counter 2 becomes the

Input device 3 set by the pulse DXS . The input device 3 is a four-bit shift register including three data bit digits and one sign bit digit, and a sign bit (not shown) is repeatedly fed in to represent the sign bit of the grand total ~ £ dy to keep. The shift register 3 has three data bit positions so that the sum of the secondary increments between them is calculated when the primary increment dx has the value zero.

The total ^ dy of the set in the shift register 3 secondary increments is added to the contents of the V-ReJJisters to calculate an integrated value. A predetermined weight relationship has been previously set between the secondary increments and the previous value so that the addition thereof is performed in accordance with this relationship. The number L is in register 4 of FIG. 1 with the low

The last bit position of the total sum Y.dy is set, which is adapted to the I-th bit position of the least significant bit position of the y register 11 (first memory), and the content of register 4 becomes counter 5 at the clock pulse C7 " _{2 is} set. The counter 5 is counted down by the clock pulse CTj, and the following clock pulse YCP is used to shift the K register 11, and when the content of the counter 5 reaches the value zero, the counter 5 generates a carry on the C terminal ₄ to set flip-flop 48. The output of flip-flop 48

causes the gates or elements 6 and 7 to open, so that the clock pulse YCP is delivered to the shift register 3, and the total sum ^ dy is transferred to the terminal G _{2 of} the first adder 12 bit by bit from the least significant bit to the most significant bit the link 7 released. A bit at the time T ₁ of the integrated value calculated in the first adder 12 is set to the K register 11 (first memory) and at the same time set to the second memory 16 with the same clock, and a bit of vrfy becomes the third at time T ₁

Memory 14 scanned. Accordingly, the memories 14 and 16 have data bits with the same time relationship or the same clock. That is, the data value read from the input device 3 is set to the second memory 16 via the data transmission times in the element 7 and in the first adder 12. After integration for the next bit at time T ₁₊ , the data value of third memory 14 set at time T _{t is} set in fourth memory 15, and the data bit at time 7 _{/ + 1} is set in second memory 16. Accordingly

the second adder 19 adds twice the value of the secondary increments ν dy to the value in the K register U. The fifth and sixth memories 22 and 23 are also set at the same time as the second memory 16. The data value set in the fifth memory 22 is the data value at the connection G ₁ or G _{7 of} the switch 20, this data value being a data bit which is ^{calculated one clock rate before the data bit of the secondary increments v} rfy which are used for integrated value are added and output from the third memory 14, or a

Data bit that is calculated at the same time and output from shift register 3. The output signal of the fifth memory 22 becomes the third adder unit 27 via the first exclusive-OR circuit 24 which produces a 2-j complement so that the addition or subtraction with the data value of the sixth Memory 23 in the third adder 27 is executed. The time relationship in the memories 23 and 22 set data is such that when the connection G is selected, the switch 20 at the time when the slight

The last bit of the total sum ^ dy of the secondary increments is set in the sixth memory 23, the least significant bit is set in the fifth memory 22, and when the connection G ₂ is selected, the next less significant bit is set in the fifth memory 22. This means that half or the entire value of the secondary increment is added to or subtracted from the integrated value as a Kornpensatiop.sterm. The compensation term can be used in the following ways:

As in the left column of FIG. 8, the data value set in register 34 is represented by input signals A, S, C and D which correspond to those in the middle column of FIG. 8 determine the types of operations shown. The resulting output signals at the output connections G 1 to G _{7 of} the decoder 37 ′ ind are shown in the right-hand column in FIG.
The F i g. 4 shows an example of the decoder 37 with a decoder 66, OR gates 67 to 70 and inverters 71 to 73.

In the following an example with A = B = D = "0" and C - "1" is explained, ie the connections G ₈ , G, and O ₁ 1 have the value "0" and the connection G ₁₀ has the Value "1". In this case, only the signals at the output connections G _{1 and G 5 of} the decoder 37 have the value “1”. Accordingly, signals are fed to the clear terminal of the fourth memory 15 via the OR gate 17 and to the terminal G _{5 of} the switch 20, so that

the connection G _{2 of} the second adder 19 assumes the value “0”, and the signal at connection G _{2 of} the switch 20 is output to the data input connection of the fifth memory 22. Since the signal at the input connection G _{2 of} the first exclusive-OR circuit 24 has the value "0" at this point in time, the output signal of the fifth memory 22 is output _{unchanged to the connection G 2 of} the third adder 27, so that the compensation term of - ^ dy _t is added to the integrated value. The output signal of the fifth adder 27 is set in the seventh memory 31 and, in the following cycle, to the input terminal G _{2 of} the fourth adder 39 via the second exclusive-OR circuit 32 for a quantization with the contents of the λ register 41 (eighth memory) submitted.

The compensation determined by the specific combination of the input signals A, B, C and D (see FIG. 8) is carried out in the adders 19 and 27 in FIG

Σ * ο + Σ * ⁺ Σ * ' ^{or +} γ

leads to the integrated value.

On the other hand, the primary increments set in flip-flops 28 and 29 become the primary incremental decider 30, which generates various signals.

5 shows an example of a specific circuit of the primary increment decision maker SO with AND gates 74 to 76 and OR gates 77 and 78. The output signals Q _A and Q _{4 of} the flip-flop 28 are applied to the input terminals G 1 and G ₂ submitted; the output signals Q _g and Q _{B of} the flip-flop 29 are applied to the input terminals G ₃ and G ₄ ; the integral in the buffer register 16 is output to the input connection G ₅ . If the primary increment is zero, the output terminal G ₉ produces a "1" output signal; when the primary increment is negative, the output terminal Gg produces a "1" output signal. If the primary increment is positive or negative, a "1" output will appear on output terminal G ₆ or G ₇ .

When the output signal at the output terminal G _.; occurs, ie if the primary increment has the value zero, the seventh memory 31 is cleared so that the quantization and integration are not carried out, and the feeding of the clock pulse is prevented by the inverter 9 and the AND gates 10 and 43, while the inclusion of the secondary increments for storing the total sum of the secondary increments is allowed. If the output terminal G <> has the value zero, the counter 2 is cleared by the AND gate 8 with the clock pulse CT _n. When the output signal appears at the output _{terminal G 8} , the integrated value of the seventh memory 31 is complemented by the second exclusive-OR circuit 32, and the flip-flop 40 is set to "1" so that the subtraction in the fourth adder 39 is carried out. In this way, the operations are carried out bit by bit from the least significant bit, and when the most significant bit (sign bit) of the Λ register 41 (eighth memory), the tertiary increment is generated, the AND gate 42 is generated by the clock pulse CTj ₂ closed in order to bring the hücrisiwei tigc bit (sign ßit) of the /? - Rcgistcrs4i to the value zero / u. That is, if the remainder of the integral in λ register 41 is negative, the tertiary increment -dz is generated, as will be explained in more detail below, and the content of the λ register 41 is changed to a positive value.

The presence and absence of the tertiary increment is determined by the tertiary increment decider44 determined based on the following equations:

If R,., + (Y ₁ ± yV j _y \ _c i _x . <Ο: -dz.

If R, -, + ίκ, + yV dy \ dx, > 0: 0.

If R _M + (Y ₁ ± -y VJ dyA dx, is a positive overflow: + dz.

The F i g. 6 shows an example of a specific circuit of the tertiary increment decision maker 44 with inverters 71 to 81, OR gates 82 to 84 and AND gates 85 to 88.

If z. B. the sign of the integral, which the output figure a! of the second exclusive-OR circuit 32 is positive and the sign of the remainder of the integral in the λ register 41 (eighth memory) is also positive, and when the sign of the sum thereof is negative, the tertiary increment + dz from the output terminal Gin generated as an overflow. If the sign of the integral is negative and the sign of the sum is also negative, the tertiary increment -dz is generated at the output terminal Gu.

In addition to the integration explained above, the auxiliary operation and the comparison can be carried out, by determining the contents of the first memory 11 in the manner described above.

The operations are explained in more detail below.

A JK flip-flop 47 shown in FIG. 7 has a connection G ₁ to which the value Y _d in the first memory 11 is output, and a connection G ₂ to which the clock pulse YCP is input. If the signal at terminal G ₁ assumes the value "1" (ie, if the value is other than zero) at any point in time during clocks 7 " ₄ through T ^ , Q =" 1 "is held. If the signal at connection G, the value "0" at the next clock pulse CT ₁₉ , Q = "1" is retained, but if the signal at connection Gi has the value "1" (ie, if the value is negative), Q = "0" (Q = "1"). Accordingly, if the output terminal G _{4 takes} the value "1", then this shows that the value is negative or zero, and if the output terminal G _{4 takes} the value "0", so this shows that the value is positive.On the other hand, since the buffer register 16 holds the most significant bit (sign bit »of the first memory 11 during and after the clock T _i9 , the results of the gates 35 and 36 prevent the signals X ₁ and X ₂ in Fig. 6 (ie the tertiary increment) occur, since the integral has the value zero when the output signal of the element 36 has the value "0" The output signal Si of the decoder 37 and the output signal of the second memory 16 prevent the signals X, and X _{1 from} occurring. Accordingly, either + dx or -dx occurs at the output of the decision maker 44 only if the content of the first memory 11 is positive during the comparison, and if the content of the first memory 11 does not have the value zero during the auxiliary operation. The output signal of the decision maker 44 is set in the flip-flops 45 and 46 at the clock pulse CT ₂₂ in order to generate the tertiary increment signals + DZ and - £> Z.

As follows from the above exemplary embodiments of the invention, the memories 14,15,16,20,23 and 31 for storing the input signals and sums of various data bits simultaneously in the adders processed, resulting in a high operating speed.

Furthermore, the data set in the memory at different times can be stored and different Compensations are carried out, which leads to very accurate results. With the conventional

Compensation can only be carried out by compensating ± - Xrfy.

The exemplary embodiments described above relate to series addition DD A's; Of course However, the invention can also be applied to parallel addition DDA's or a combination of series and Parallel DD A's can be used. In this case, however, one buffer register is required for each data bit. Therefore, fewer components are required when the invention is used for a series addition DD A 5 will.

In addition 5 sheets of drawings

Claims (1)

Claim: DDA computer (digital differential analyzer) consisting of input devices for inputting at least one primary increment and at least one secondary increment and a computing device for forming a tertiary increment on the basis of the input of the primary and secondary increments,
characterized in that the computing device consists of a first adder (12) for performing an integration operation by adding the secondary increment, which is supplied by the input device (3) to the content of a first memory (Jl), in in which the value of the integrand is stored, a second memory (16) for the temporary storage of the result from the first adder (12) is issued, a third memory (14) for the temporary storage of the secondary increment received from the input device (3) is delivered, a fourth memory (15) for the temporary storage of the content from the third memory (14) is delivered, a fifth memory (22) for the temporary storage of either the secondary increment that from the input device (3) or the content of the third memory (14), which this secondary increment cached, the selection between the two values (from 3 or 14) through a switch (20) takes place, a second adder (19) for adding the content of the value stored in the fourth memory (15) to the value stored in the second memory (16), a sixth memory (23) for temporarily storing the values formed in the second adder (19) Total, a third adder (27) for adding or subtracting the content of the fifth memory (22) to or from the content of the sixth memory (23), the content of the fifth memory (22) via a first exclusive-or circle (24) is directed, a seventh memory (31) for the temporary storage of the result from the third adder (27) is issued, a fourth adder (39) to which the value stored in the seventh memory (31) and the primary increment are fed via a second exclusive-or circuit (32) and, in addition, the residual value of the integration in an eighth memory (41) Operation for the formation of the tertiary increment, and
from a control device, consisting of a register (34) and a decoder (37), for controlling the third, fourth and fifth memories (14,15,22), the switch (20) and the first exclusive-or circuit ( 24) for parallel and independent control of the operations in the first, second and third adding units.