DE2545921A1 - Binaere halbleiter-speicherzelle - Google Patents
Binaere halbleiter-speicherzelleInfo
- Publication number
- DE2545921A1 DE2545921A1 DE19752545921 DE2545921A DE2545921A1 DE 2545921 A1 DE2545921 A1 DE 2545921A1 DE 19752545921 DE19752545921 DE 19752545921 DE 2545921 A DE2545921 A DE 2545921A DE 2545921 A1 DE2545921 A1 DE 2545921A1
- Authority
- DE
- Germany
- Prior art keywords
- output
- memory cell
- transistor
- memory
- cell according
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 239000004065 semiconductor Substances 0.000 title claims description 9
- 210000000352 storage cell Anatomy 0.000 title description 5
- 210000004027 cell Anatomy 0.000 description 38
- 230000000694 effects Effects 0.000 description 4
- 230000006870 function Effects 0.000 description 4
- 238000011161 development Methods 0.000 description 3
- 230000018109 developmental process Effects 0.000 description 3
- 239000011159 matrix material Substances 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 101100136648 Mus musculus Pign gene Proteins 0.000 description 2
- 239000000872 buffer Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000001419 dependent effect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000001144 postural effect Effects 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/39—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using thyristors or the avalanche or negative resistance type, e.g. PNPN, SCR, SCS, UJT
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/35—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar semiconductor devices with more than two PN junctions, or more than three electrodes, or more than one electrode connected to the same conductivity region
- H03K3/352—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar semiconductor devices with more than two PN junctions, or more than three electrodes, or more than one electrode connected to the same conductivity region the devices being thyristors
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Static Random-Access Memory (AREA)
- Semiconductor Memories (AREA)
- Read Only Memory (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US522659A US3918033A (en) | 1974-11-11 | 1974-11-11 | SCR memory cell |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| DE2545921A1 true DE2545921A1 (de) | 1976-05-13 |
Family
ID=24081783
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DE19752545921 Withdrawn DE2545921A1 (de) | 1974-11-11 | 1975-10-14 | Binaere halbleiter-speicherzelle |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US3918033A (https=) |
| JP (1) | JPS574998B2 (https=) |
| CA (1) | CA1058320A (https=) |
| DE (1) | DE2545921A1 (https=) |
| FR (1) | FR2290731A1 (https=) |
| GB (1) | GB1521099A (https=) |
| IT (1) | IT1042692B (https=) |
Families Citing this family (30)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4031413A (en) * | 1975-01-10 | 1977-06-21 | Hitachi, Ltd. | Memory circuit |
| JPS582435B2 (ja) * | 1975-08-09 | 1983-01-17 | 株式会社日立製作所 | キオクカイロ |
| JPS52153630A (en) * | 1976-06-16 | 1977-12-20 | Matsushita Electric Ind Co Ltd | Semiconductor memory device |
| FR2364528A1 (fr) * | 1976-09-10 | 1978-04-07 | Thomson Csf | Cellule de memoire a transistor tetrode et circuit de memoire comportant de telles cellules |
| US4409673A (en) * | 1980-12-31 | 1983-10-11 | Ibm Corporation | Single isolation cell for DC stable memory |
| GB2247550B (en) * | 1990-06-29 | 1994-08-03 | Digital Equipment Corp | Bipolar transistor memory cell and method |
| DE4041260A1 (de) * | 1990-12-21 | 1992-07-02 | Messerschmitt Boelkow Blohm | Ausleseschaltung fuer eine statische speicherzelle |
| US6229161B1 (en) | 1998-06-05 | 2001-05-08 | Stanford University | Semiconductor capacitively-coupled NDR device and its applications in high-density high-speed memories and in power switches |
| US6690038B1 (en) | 1999-06-05 | 2004-02-10 | T-Ram, Inc. | Thyristor-based device over substrate surface |
| US6727528B1 (en) | 2001-03-22 | 2004-04-27 | T-Ram, Inc. | Thyristor-based device including trench dielectric isolation for thyristor-body regions |
| US7456439B1 (en) | 2001-03-22 | 2008-11-25 | T-Ram Semiconductor, Inc. | Vertical thyristor-based memory with trench isolation and its method of fabrication |
| US6804162B1 (en) | 2001-04-05 | 2004-10-12 | T-Ram, Inc. | Read-modify-write memory using read-or-write banks |
| AU2002252593A1 (en) * | 2001-04-05 | 2002-10-21 | Hyun-Jin Cho | Data restore in thyristor-based memory |
| US6576959B2 (en) * | 2001-04-10 | 2003-06-10 | Texas Instruments Incorporated | Device and method of low voltage SCR protection for high voltage failsafe ESD applications |
| US6583452B1 (en) | 2001-12-17 | 2003-06-24 | T-Ram, Inc. | Thyristor-based device having extended capacitive coupling |
| US6832300B2 (en) | 2002-03-20 | 2004-12-14 | Hewlett-Packard Development Company, L.P. | Methods and apparatus for control of asynchronous cache |
| US7221586B2 (en) | 2002-07-08 | 2007-05-22 | Micron Technology, Inc. | Memory utilizing oxide nanolaminates |
| US6865407B2 (en) * | 2002-07-11 | 2005-03-08 | Optical Sensors, Inc. | Calibration technique for non-invasive medical devices |
| US6903969B2 (en) * | 2002-08-30 | 2005-06-07 | Micron Technology Inc. | One-device non-volatile random access memory cell |
| US6917078B2 (en) * | 2002-08-30 | 2005-07-12 | Micron Technology Inc. | One transistor SOI non-volatile random access memory cell |
| US6888200B2 (en) * | 2002-08-30 | 2005-05-03 | Micron Technology Inc. | One transistor SOI non-volatile random access memory cell |
| US7042027B2 (en) * | 2002-08-30 | 2006-05-09 | Micron Technology, Inc. | Gated lateral thyristor-based random access memory cell (GLTRAM) |
| US6690039B1 (en) * | 2002-10-01 | 2004-02-10 | T-Ram, Inc. | Thyristor-based device that inhibits undesirable conductive channel formation |
| US8125003B2 (en) * | 2003-07-02 | 2012-02-28 | Micron Technology, Inc. | High-performance one-transistor memory cell |
| US6944051B1 (en) * | 2003-10-29 | 2005-09-13 | T-Ram, Inc. | Data restore in thryistor based memory devices |
| US7145186B2 (en) * | 2004-08-24 | 2006-12-05 | Micron Technology, Inc. | Memory cell with trenched gated thyristor |
| US7781797B2 (en) * | 2006-06-29 | 2010-08-24 | International Business Machines Corporation | One-transistor static random access memory with integrated vertical PNPN device |
| US8035126B2 (en) * | 2007-10-29 | 2011-10-11 | International Business Machines Corporation | One-transistor static random access memory with integrated vertical PNPN device |
| US7940560B2 (en) * | 2008-05-29 | 2011-05-10 | Advanced Micro Devices, Inc. | Memory cells, memory devices and integrated circuits incorporating the same |
| KR102226206B1 (ko) * | 2020-02-06 | 2021-03-11 | 포항공과대학교 산학협력단 | 이중 pn 접합을 포함하는 메모리 소자 및 그 구동방법 |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3375502A (en) * | 1964-11-10 | 1968-03-26 | Litton Systems Inc | Dynamic memory using controlled semiconductors |
| US3540002A (en) * | 1968-02-26 | 1970-11-10 | Ibm | Content addressable memory |
| US3697962A (en) * | 1970-11-27 | 1972-10-10 | Ibm | Two device monolithic bipolar memory array |
-
1974
- 1974-11-11 US US522659A patent/US3918033A/en not_active Expired - Lifetime
-
1975
- 1975-09-19 IT IT27414/75A patent/IT1042692B/it active
- 1975-09-19 FR FR7529326A patent/FR2290731A1/fr active Granted
- 1975-09-25 CA CA236,363A patent/CA1058320A/en not_active Expired
- 1975-10-07 GB GB40910/75A patent/GB1521099A/en not_active Expired
- 1975-10-14 DE DE19752545921 patent/DE2545921A1/de not_active Withdrawn
- 1975-11-05 JP JP13221175A patent/JPS574998B2/ja not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| US3918033A (en) | 1975-11-04 |
| GB1521099A (en) | 1978-08-09 |
| CA1058320A (en) | 1979-07-10 |
| JPS5171035A (https=) | 1976-06-19 |
| JPS574998B2 (https=) | 1982-01-28 |
| IT1042692B (it) | 1980-01-30 |
| FR2290731B1 (https=) | 1978-04-07 |
| FR2290731A1 (fr) | 1976-06-04 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| 8139 | Disposal/non-payment of the annual fee |