DE2536108A1 - Kantenbegrenzung bei halbleiterscheibchen - Google Patents

Kantenbegrenzung bei halbleiterscheibchen

Info

Publication number
DE2536108A1
DE2536108A1 DE19752536108 DE2536108A DE2536108A1 DE 2536108 A1 DE2536108 A1 DE 2536108A1 DE 19752536108 DE19752536108 DE 19752536108 DE 2536108 A DE2536108 A DE 2536108A DE 2536108 A1 DE2536108 A1 DE 2536108A1
Authority
DE
Germany
Prior art keywords
transition
grooves
mesa
junction
disc
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
DE19752536108
Other languages
German (de)
English (en)
Inventor
Samuel Ponczak
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
RCA Corp
Original Assignee
RCA Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by RCA Corp filed Critical RCA Corp
Publication of DE2536108A1 publication Critical patent/DE2536108A1/de
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0661Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604Chemical etching

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Ceramic Engineering (AREA)
  • Weting (AREA)
  • Bipolar Transistors (AREA)
DE19752536108 1974-08-21 1975-08-13 Kantenbegrenzung bei halbleiterscheibchen Pending DE2536108A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US49928874A 1974-08-21 1974-08-21

Publications (1)

Publication Number Publication Date
DE2536108A1 true DE2536108A1 (de) 1976-03-11

Family

ID=23984661

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19752536108 Pending DE2536108A1 (de) 1974-08-21 1975-08-13 Kantenbegrenzung bei halbleiterscheibchen

Country Status (7)

Country Link
JP (1) JPS5146076A (xx)
BE (1) BE832633A (xx)
CA (1) CA1038969A (xx)
DE (1) DE2536108A1 (xx)
FR (1) FR2282722A1 (xx)
GB (1) GB1471116A (xx)
IT (1) IT1040004B (xx)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0379208A2 (en) * 1989-01-20 1990-07-25 Fujitsu Limited A method for producing a device having an insulator sandwiched between two semiconductor layers

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL7607298A (nl) * 1976-07-02 1978-01-04 Philips Nv Werkwijze voor het vervaardigen van een inrichting en inrichting vervaardigd volgens de werkwijze.
FR2410366A1 (fr) * 1977-11-29 1979-06-22 Radiotechnique Compelec Transistor de type mesa et procede de realisation de ce transistor
JPS5895553A (ja) * 1981-12-01 1983-06-07 Nippon Shokubai Kagaku Kogyo Co Ltd 耐熱衝撃性の改良されたハニカム触媒の製造方法
DE3422051C2 (de) * 1984-06-14 1986-06-26 Brown, Boveri & Cie Ag, 6800 Mannheim Silizium-Halbleiterbauelement mit ätztechnisch hergestellter Randkontur und Verfahren zur Herstellung dieses Bauelements
GB2176338A (en) * 1985-06-06 1986-12-17 Marconi Electronic Devices Edge contouring in a semiconductor device
JPH03129854A (ja) * 1989-10-16 1991-06-03 Toshiba Corp 半導体装置の製造方法
DE19536438A1 (de) * 1995-09-29 1997-04-03 Siemens Ag Halbleiterbauelement und Herstellverfahren

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0379208A2 (en) * 1989-01-20 1990-07-25 Fujitsu Limited A method for producing a device having an insulator sandwiched between two semiconductor layers
EP0379208A3 (en) * 1989-01-20 1991-03-13 Fujitsu Limited A method for producing a device having an insulator sandwiched between two semiconductor layers

Also Published As

Publication number Publication date
FR2282722A1 (fr) 1976-03-19
GB1471116A (en) 1977-04-21
JPS5227033B2 (xx) 1977-07-18
IT1040004B (it) 1979-12-20
JPS5146076A (ja) 1976-04-20
BE832633A (fr) 1975-12-16
CA1038969A (en) 1978-09-19

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