DE2355471A1 - Aus mehreren ebenen bestehende packung fuer halbleiterschaltungen - Google Patents

Aus mehreren ebenen bestehende packung fuer halbleiterschaltungen

Info

Publication number
DE2355471A1
DE2355471A1 DE19732355471 DE2355471A DE2355471A1 DE 2355471 A1 DE2355471 A1 DE 2355471A1 DE 19732355471 DE19732355471 DE 19732355471 DE 2355471 A DE2355471 A DE 2355471A DE 2355471 A1 DE2355471 A1 DE 2355471A1
Authority
DE
Germany
Prior art keywords
substrate
lines
substrates
pack according
electrical
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
DE19732355471
Other languages
German (de)
English (en)
Inventor
Philip A Tatusko
Richard A Williams
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of DE2355471A1 publication Critical patent/DE2355471A1/de
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/183—Components mounted in and supported by recessed areas of the printed circuit board
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5385—Assembly of a plurality of insulating substrates
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0286—Programmable, customizable or modifiable circuits
    • H05K1/0287—Programmable, customizable or modifiable circuits having an universal lay-out, e.g. pad or land grid patterns or mesh patterns
    • H05K1/0289—Programmable, customizable or modifiable circuits having an universal lay-out, e.g. pad or land grid patterns or mesh patterns having a matrix lay-out, i.e. having selectively interconnectable sets of X-conductors and Y-conductors in different planes
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits
    • H05K1/144—Stacked arrangements of planar printed circuit boards
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Combinations Of Printed Boards (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Manufacturing Of Printed Wiring (AREA)
DE19732355471 1972-12-18 1973-11-07 Aus mehreren ebenen bestehende packung fuer halbleiterschaltungen Pending DE2355471A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US31632772A 1972-12-18 1972-12-18

Publications (1)

Publication Number Publication Date
DE2355471A1 true DE2355471A1 (de) 1974-06-20

Family

ID=23228576

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19732355471 Pending DE2355471A1 (de) 1972-12-18 1973-11-07 Aus mehreren ebenen bestehende packung fuer halbleiterschaltungen

Country Status (5)

Country Link
US (1) US3777221A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
JP (1) JPS589597B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
DE (1) DE2355471A1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
FR (1) FR2210823B1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
GB (1) GB1444814A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3201296A1 (de) * 1982-01-18 1983-07-28 Institut elektrodinamiki Akademii Nauk Ukrainskoj SSR, Kiev Transistoranordnung
DE3409146A1 (de) * 1984-03-13 1985-09-19 Siemens AG, 1000 Berlin und 8000 München Optoelektronisches mudul

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US3952231A (en) * 1974-09-06 1976-04-20 International Business Machines Corporation Functional package for complex electronic systems with polymer-metal laminates and thermal transposer
JPS541159B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) * 1974-10-21 1979-01-20
JPS5333856U (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) * 1976-08-30 1978-03-24
DE2826840A1 (de) * 1977-06-20 1979-01-11 Hitachi Ltd Elektronisches geraet und verfahren zu seiner herstellung
JPS594873B2 (ja) * 1978-09-26 1984-02-01 松下電器産業株式会社 印刷配線板
US4254445A (en) * 1979-05-07 1981-03-03 International Business Machines Corporation Discretionary fly wire chip interconnection
US4283755A (en) * 1980-02-05 1981-08-11 The United States Of America As Represented By The Secretary Of The Air Force Modulator multilayer detector
GB2083285B (en) * 1980-02-12 1984-08-15 Mostek Corp Over/under dual in-line chip package
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FR2511544A1 (fr) * 1981-08-14 1983-02-18 Dassault Electronique Module electronique pour carte de transactions automatiques et carte equipee d'un tel module
US4489364A (en) * 1981-12-31 1984-12-18 International Business Machines Corporation Chip carrier with embedded engineering change lines with severable periodically spaced bridging connectors on the chip supporting surface
US4450029A (en) * 1982-01-13 1984-05-22 Elxsi Backplane fabrication method
US4549200A (en) * 1982-07-08 1985-10-22 International Business Machines Corporation Repairable multi-level overlay system for semiconductor device
US4536638A (en) * 1982-09-30 1985-08-20 Witold Krynicki Chip assembly
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US4512509A (en) * 1983-02-25 1985-04-23 At&T Technologies, Inc. Technique for bonding a chip carrier to a metallized substrate
US4630172A (en) * 1983-03-09 1986-12-16 Printed Circuits International Semiconductor chip carrier package with a heat sink
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US4722914A (en) * 1984-05-30 1988-02-02 Motorola Inc. Method of making a high density IC module assembly
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US4585157A (en) * 1985-04-04 1986-04-29 General Motors Corporation Tape bonding of two integrated circuits into one tape frame
US4659931A (en) * 1985-05-08 1987-04-21 Grumman Aerospace Corporation High density multi-layered integrated circuit package
JPS61296800A (ja) * 1985-06-25 1986-12-27 日本電気株式会社 設計変更用電極
US4764644A (en) * 1985-09-30 1988-08-16 Microelectronics Center Of North Carolina Microelectronics apparatus
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DE3677601D1 (de) * 1986-08-22 1991-03-28 Ibm Deutschland Integriertes verdrahtungssystem fuer sehr hochintegrierte schaltungen.
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JPH038352A (ja) * 1989-06-06 1991-01-16 Shinko Electric Ind Co Ltd 半導体装置
JPH0371661A (ja) * 1989-08-11 1991-03-27 Fujitsu Ltd 電子回路パッケージ及びその製造方法
US5041943A (en) * 1989-11-06 1991-08-20 Allied-Signal Inc. Hermetically sealed printed circuit board
US5861897A (en) * 1991-01-19 1999-01-19 Canon Kabushiki Kaisha Inkjet recording apparatus with a memory device disposed substantially within boundaries if a recording head unit
US5322812A (en) * 1991-03-20 1994-06-21 Crosspoint Solutions, Inc. Improved method of fabricating antifuses in an integrated circuit device and resulting structure
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DE69405832T2 (de) * 1993-07-28 1998-02-05 Whitaker Corp Von der Peripherie-unabhängiges präzises Positionsglied für einen Halbleiterchip und Herstellungsverfahren dafür
US5617131A (en) * 1993-10-28 1997-04-01 Kyocera Corporation Image device having a spacer with image arrays disposed in holes thereof
US5544018A (en) * 1994-04-13 1996-08-06 Microelectronics And Computer Technology Corporation Electrical interconnect device with customizeable surface layer and interwoven signal lines
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JPS5151000Y2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) * 1971-03-27 1976-12-07

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3201296A1 (de) * 1982-01-18 1983-07-28 Institut elektrodinamiki Akademii Nauk Ukrainskoj SSR, Kiev Transistoranordnung
DE3409146A1 (de) * 1984-03-13 1985-09-19 Siemens AG, 1000 Berlin und 8000 München Optoelektronisches mudul

Also Published As

Publication number Publication date
FR2210823B1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1978-01-06
US3777221A (en) 1973-12-04
FR2210823A1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1974-07-12
JPS589597B2 (ja) 1983-02-22
GB1444814A (en) 1976-08-04
JPS4989162A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1974-08-26

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