DE19845004C2 - DRAM-Zellenanordnung und Verfahren zu deren Herstellung - Google Patents

DRAM-Zellenanordnung und Verfahren zu deren Herstellung

Info

Publication number
DE19845004C2
DE19845004C2 DE19845004A DE19845004A DE19845004C2 DE 19845004 C2 DE19845004 C2 DE 19845004C2 DE 19845004 A DE19845004 A DE 19845004A DE 19845004 A DE19845004 A DE 19845004A DE 19845004 C2 DE19845004 C2 DE 19845004C2
Authority
DE
Germany
Prior art keywords
produced
parts
depressions
structures
spacers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE19845004A
Other languages
German (de)
English (en)
Other versions
DE19845004A1 (de
Inventor
Josef Willer
Franz Hofmann
Till Schloesser
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Polaris Innovations Ltd
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to DE19845004A priority Critical patent/DE19845004C2/de
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Priority to JP2000572936A priority patent/JP3805624B2/ja
Priority to PCT/DE1999/002939 priority patent/WO2000019528A1/de
Priority to KR10-2001-7003837A priority patent/KR100436413B1/ko
Priority to EP99955719A priority patent/EP1129483A1/de
Priority to US09/806,427 priority patent/US6492221B1/en
Priority to TW088116496A priority patent/TW452831B/zh
Publication of DE19845004A1 publication Critical patent/DE19845004A1/de
Application granted granted Critical
Publication of DE19845004C2 publication Critical patent/DE19845004C2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate
    • H10B12/0383—Making the capacitor or connections thereto the capacitor being in a trench in the substrate wherein the transistor is vertical
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H10B12/053—Making the transistor the transistor being at least partially in a trench in the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/39—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor and the transistor being in a same trench
    • H10B12/395—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor and the transistor being in a same trench the transistor being vertical

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
DE19845004A 1998-09-30 1998-09-30 DRAM-Zellenanordnung und Verfahren zu deren Herstellung Expired - Fee Related DE19845004C2 (de)

Priority Applications (7)

Application Number Priority Date Filing Date Title
DE19845004A DE19845004C2 (de) 1998-09-30 1998-09-30 DRAM-Zellenanordnung und Verfahren zu deren Herstellung
PCT/DE1999/002939 WO2000019528A1 (de) 1998-09-30 1999-09-15 Dram-zellenanordnung und verfahren zu deren herstellung
KR10-2001-7003837A KR100436413B1 (ko) 1998-09-30 1999-09-15 디램 셀 시스템 및 그의 제조방법
EP99955719A EP1129483A1 (de) 1998-09-30 1999-09-15 Dram-zellenanordnung und verfahren zu deren herstellung
JP2000572936A JP3805624B2 (ja) 1998-09-30 1999-09-15 Ｄｒａｍセル装置およびその製造方法
US09/806,427 US6492221B1 (en) 1998-09-30 1999-09-15 DRAM cell arrangement
TW088116496A TW452831B (en) 1998-09-30 1999-09-27 DRAM-cells arrangement and its production method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19845004A DE19845004C2 (de) 1998-09-30 1998-09-30 DRAM-Zellenanordnung und Verfahren zu deren Herstellung

Publications (2)

Publication Number Publication Date
DE19845004A1 DE19845004A1 (de) 2000-04-13
DE19845004C2 true DE19845004C2 (de) 2002-06-13

Family

ID=7882901

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19845004A Expired - Fee Related DE19845004C2 (de) 1998-09-30 1998-09-30 DRAM-Zellenanordnung und Verfahren zu deren Herstellung

Country Status (7)

Country Link
US (1) US6492221B1 (zh)
EP (1) EP1129483A1 (zh)
JP (1) JP3805624B2 (zh)
KR (1) KR100436413B1 (zh)
DE (1) DE19845004C2 (zh)
TW (1) TW452831B (zh)
WO (1) WO2000019528A1 (zh)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10024876A1 (de) 2000-05-16 2001-11-29 Infineon Technologies Ag Vertikaler Transistor
US6339241B1 (en) * 2000-06-23 2002-01-15 International Business Machines Corporation Structure and process for 6F2 trench capacitor DRAM cell with vertical MOSFET and 3F bitline pitch
DE10038728A1 (de) * 2000-07-31 2002-02-21 Infineon Technologies Ag Halbleiterspeicher-Zellenanordnung und Verfahren zu deren Herstellung
US6509624B1 (en) * 2000-09-29 2003-01-21 International Business Machines Corporation Semiconductor fuses and antifuses in vertical DRAMS
JP3549499B2 (ja) * 2001-07-04 2004-08-04 松下電器産業株式会社 半導体集積回路装置ならびにｄ／ａ変換装置およびａ／ｄ変換装置
DE10362018B4 (de) 2003-02-14 2007-03-08 Infineon Technologies Ag Anordnung und Verfahren zur Herstellung von vertikalen Transistorzellen und transistorgesteuerten Speicherzellen
WO2007027169A2 (en) * 2005-08-30 2007-03-08 University Of South Florida Method of manufacturing silicon topological capacitors
BRPI0515108A (pt) * 2004-09-10 2008-07-01 Syngenta Ltd composto, composições para controlar e evitar microorganismos patogênicos vegetais, e para tratar uma infecção fúngica, e, métodos para controlar ou evitar infestação de plantas cultivadas por microorganismos patogêncos, infestação de material de propagação vegetal por microorganismos patogênicos, e infestação de um material técnico por microorganismos patogênicos, para tratar uma infecção fúngica em um paciente em necessidade deste, e para fabricar um composto
US7326611B2 (en) * 2005-02-03 2008-02-05 Micron Technology, Inc. DRAM arrays, vertical transistor structures and methods of forming transistor structures and DRAM arrays
JP5060413B2 (ja) * 2008-07-15 2012-10-31 株式会社東芝 半導体記憶装置
US9171847B1 (en) 2014-10-02 2015-10-27 Inotera Memories, Inc. Semiconductor structure
CN111386229B (zh) 2017-12-15 2021-12-24 赫斯基注塑系统有限公司 用于容器的封闭盖
CN111834364B (zh) * 2019-04-19 2023-08-29 华邦电子股份有限公司 动态随机存取存储器
CN113517232B (zh) * 2021-07-08 2023-09-26 长鑫存储技术有限公司 半导体器件结构及制备方法

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0852396A2 (en) * 1996-12-20 1998-07-08 Siemens Aktiengesellschaft Memory cell that includes a vertical transistor and a trench capacitor

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62274771A (ja) 1986-05-23 1987-11-28 Hitachi Ltd 半導体メモリ
US5008214A (en) 1988-06-03 1991-04-16 Texas Instruments Incorporated Method of making crosspoint dynamic RAM cell array with overlapping wordlines and folded bitlines
JPH0319363A (ja) 1989-06-16 1991-01-28 Toshiba Corp 半導体記憶装置
US5214603A (en) 1991-08-05 1993-05-25 International Business Machines Corporation Folded bitline, ultra-high density dynamic random access memory having access transistors stacked above trench storage capacitors
KR0141218B1 (ko) 1993-11-24 1998-07-15 윤종용 고집적 반도체장치의 제조방법
DE19718721C2 (de) * 1997-05-02 1999-10-07 Siemens Ag DRAM-Zellenanordnung und Verfahren zu deren Herstellung
TW429620B (en) * 1997-06-27 2001-04-11 Siemens Ag SRAM cell arrangement and method for its fabrication
EP0899790A3 (de) * 1997-08-27 2006-02-08 Infineon Technologies AG DRAM-Zellanordnung und Verfahren zu deren Herstellung
EP0924766B1 (de) * 1997-12-17 2008-02-20 Qimonda AG Speicherzellenanordnung und Verfahren zu deren Herstellung

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0852396A2 (en) * 1996-12-20 1998-07-08 Siemens Aktiengesellschaft Memory cell that includes a vertical transistor and a trench capacitor

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
IEDM 1995, S. 661-664 *

Also Published As

Publication number Publication date
WO2000019528A9 (de) 2000-11-09
US6492221B1 (en) 2002-12-10
KR20010079925A (ko) 2001-08-22
KR100436413B1 (ko) 2004-06-16
TW452831B (en) 2001-09-01
JP2003521103A (ja) 2003-07-08
EP1129483A1 (de) 2001-09-05
WO2000019528A1 (de) 2000-04-06
JP3805624B2 (ja) 2006-08-02
DE19845004A1 (de) 2000-04-13

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Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
8127 New person/name/address of the applicant

Owner name: INFINEON TECHNOLOGIES AG, 81669 MUENCHEN, DE

D2 Grant after examination
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: QIMONDA AG, 81739 MUENCHEN, DE

R081 Change of applicant/patentee

Owner name: INFINEON TECHNOLOGIES AG, DE

Free format text: FORMER OWNER: QIMONDA AG, 81739 MUENCHEN, DE

Owner name: POLARIS INNOVATIONS LTD., IE

Free format text: FORMER OWNER: QIMONDA AG, 81739 MUENCHEN, DE

R081 Change of applicant/patentee

Owner name: POLARIS INNOVATIONS LTD., IE

Free format text: FORMER OWNER: INFINEON TECHNOLOGIES AG, 85579 NEUBIBERG, DE

R119 Application deemed withdrawn, or ip right lapsed, due to non-payment of renewal fee