DE19840248A1 - Schaltungschip mit spezifischer Anschlußflächenanordnung - Google Patents

Schaltungschip mit spezifischer Anschlußflächenanordnung

Info

Publication number
DE19840248A1
DE19840248A1 DE1998140248 DE19840248A DE19840248A1 DE 19840248 A1 DE19840248 A1 DE 19840248A1 DE 1998140248 DE1998140248 DE 1998140248 DE 19840248 A DE19840248 A DE 19840248A DE 19840248 A1 DE19840248 A1 DE 19840248A1
Authority
DE
Germany
Prior art keywords
circuit chip
circuit
connection
integrated circuit
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
DE1998140248
Other languages
German (de)
English (en)
Inventor
Andreas Plettner
Karl Haberger
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fraunhofer Gesellschaft zur Forderung der Angewandten Forschung eV
Original Assignee
Fraunhofer Gesellschaft zur Forderung der Angewandten Forschung eV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fraunhofer Gesellschaft zur Forderung der Angewandten Forschung eV filed Critical Fraunhofer Gesellschaft zur Forderung der Angewandten Forschung eV
Priority to DE1998140248 priority Critical patent/DE19840248A1/de
Priority to PCT/EP1999/006471 priority patent/WO2000014681A2/fr
Publication of DE19840248A1 publication Critical patent/DE19840248A1/de
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Wire Bonding (AREA)
DE1998140248 1998-09-03 1998-09-03 Schaltungschip mit spezifischer Anschlußflächenanordnung Withdrawn DE19840248A1 (de)

Priority Applications (2)

Application Number Priority Date Filing Date Title
DE1998140248 DE19840248A1 (de) 1998-09-03 1998-09-03 Schaltungschip mit spezifischer Anschlußflächenanordnung
PCT/EP1999/006471 WO2000014681A2 (fr) 1998-09-03 1999-09-02 Puce de connexion a structure superficielle de raccordement specifique

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE1998140248 DE19840248A1 (de) 1998-09-03 1998-09-03 Schaltungschip mit spezifischer Anschlußflächenanordnung

Publications (1)

Publication Number Publication Date
DE19840248A1 true DE19840248A1 (de) 2000-03-16

Family

ID=7879729

Family Applications (1)

Application Number Title Priority Date Filing Date
DE1998140248 Withdrawn DE19840248A1 (de) 1998-09-03 1998-09-03 Schaltungschip mit spezifischer Anschlußflächenanordnung

Country Status (2)

Country Link
DE (1) DE19840248A1 (fr)
WO (1) WO2000014681A2 (fr)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10120408A1 (de) * 2001-04-25 2002-10-31 Infineon Technologies Ag Elektronisches Bauteil mit Halbleiterchips und elektronische Baugruppe aus gestapelten Halbleiterchips
DE10161043A1 (de) * 2001-12-12 2003-07-03 Infineon Technologies Ag Chipanordnung
US6715675B1 (en) 2000-11-16 2004-04-06 Eldat Communication Ltd. Electronic shelf label systems and methods
US6770186B2 (en) 2001-11-13 2004-08-03 Eldat Communication Ltd. Rechargeable hydrogen-fueled motor vehicle
DE10358282A1 (de) * 2003-12-12 2005-07-28 Georg Bernitz Bauelement und Verfahren zu dessen Herstellung
US7074509B2 (en) 2001-11-13 2006-07-11 Eldat Communication Ltd. Hydrogen generators for fuel cells
DE102006048583B3 (de) * 2006-10-13 2008-01-31 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Bauelement mit mehreren Kontaktflächen und ein Kontaktierungsverfahren
US7537963B2 (en) 2003-11-28 2009-05-26 Georg Bernitz Device and method for manufacturing the same
US20110316156A1 (en) * 2010-06-24 2011-12-29 Stats Chippac, Ltd. Semiconductor Device and Method of Forming RDL Along Sloped Side Surface of Semiconductor Die for Z-Direction Interconnect

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4249299A (en) * 1979-03-05 1981-02-10 Hughes Aircraft Company Edge-around leads for backside connections to silicon circuit die
CH661816A5 (de) * 1980-11-21 1987-08-14 Gao Ges Automation Org Traeger mit einem ic-baustein.
WO1993018485A1 (fr) * 1992-03-09 1993-09-16 Control Module Inc. Element d'identification a dispositif a memoire integre
WO1997035273A2 (fr) * 1996-03-15 1997-09-25 David Finn Carte a puce
EP0588944B1 (fr) * 1991-06-05 2003-01-02 Algernon Promotions, Inc. Repondeur miniature ameliore

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59229686A (ja) * 1983-06-09 1984-12-24 Toshiba Corp Ｉｃカ−ド
NL9200885A (nl) * 1992-05-20 1993-12-16 Nedap Nv Wegwerp chipkaart voor eenmalig gebruik.
US5739554A (en) * 1995-05-08 1998-04-14 Cree Research, Inc. Double heterojunction light emitting diode with gallium nitride active layer
JP3150575B2 (ja) * 1995-07-18 2001-03-26 沖電気工業株式会社 タグ装置及びその製造方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4249299A (en) * 1979-03-05 1981-02-10 Hughes Aircraft Company Edge-around leads for backside connections to silicon circuit die
CH661816A5 (de) * 1980-11-21 1987-08-14 Gao Ges Automation Org Traeger mit einem ic-baustein.
EP0588944B1 (fr) * 1991-06-05 2003-01-02 Algernon Promotions, Inc. Repondeur miniature ameliore
WO1993018485A1 (fr) * 1992-03-09 1993-09-16 Control Module Inc. Element d'identification a dispositif a memoire integre
WO1997035273A2 (fr) * 1996-03-15 1997-09-25 David Finn Carte a puce

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
JP 3-51196 A, In: Patent Abstracts of Japan *

Cited By (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7040536B2 (en) 2000-11-16 2006-05-09 Eldat Communication Ltd. Electronic shelf label systems and methods
US6715675B1 (en) 2000-11-16 2004-04-06 Eldat Communication Ltd. Electronic shelf label systems and methods
EP2196983A1 (fr) 2000-11-16 2010-06-16 Eldat Communications Ltd. Systèmes et méthodes relatifs aux étiquettes électroniques
US8350364B2 (en) 2001-04-25 2013-01-08 Qimonda Ag Electronic component with semiconductor chips, electronic assembly composed of stacked semiconductor chips, and methods for producing an electronic component and an electronic assembly
US7342320B2 (en) 2001-04-25 2008-03-11 Infineon Technologies Ag Electronic component with semiconductor chips, electronic assembly composed of stacked semiconductor chips, and methods for producing an electronic component and an electronic assembly
DE10120408A1 (de) * 2001-04-25 2002-10-31 Infineon Technologies Ag Elektronisches Bauteil mit Halbleiterchips und elektronische Baugruppe aus gestapelten Halbleiterchips
DE10120408B4 (de) * 2001-04-25 2006-02-02 Infineon Technologies Ag Elektronisches Bauteil mit einem Halbleiterchip, elektronische Baugruppe aus gestapelten Halbleiterchips und Verfahren zu deren Herstellung
US7074509B2 (en) 2001-11-13 2006-07-11 Eldat Communication Ltd. Hydrogen generators for fuel cells
US6770186B2 (en) 2001-11-13 2004-08-03 Eldat Communication Ltd. Rechargeable hydrogen-fueled motor vehicle
US8071242B2 (en) 2001-11-13 2011-12-06 Eldat Communication Ltd. Hydrogen generators for fuel cells
DE10161043B4 (de) * 2001-12-12 2005-12-15 Infineon Technologies Ag Chipanordnung
DE10161043A1 (de) * 2001-12-12 2003-07-03 Infineon Technologies Ag Chipanordnung
US7537963B2 (en) 2003-11-28 2009-05-26 Georg Bernitz Device and method for manufacturing the same
DE10358282A1 (de) * 2003-12-12 2005-07-28 Georg Bernitz Bauelement und Verfahren zu dessen Herstellung
DE102006048583B3 (de) * 2006-10-13 2008-01-31 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Bauelement mit mehreren Kontaktflächen und ein Kontaktierungsverfahren
US8331100B2 (en) 2006-10-13 2012-12-11 Fraunhofer-Gesellschaft Zur Foerderung Der Angewandten Forschung E.V. Device having several contact areas
US20110316156A1 (en) * 2010-06-24 2011-12-29 Stats Chippac, Ltd. Semiconductor Device and Method of Forming RDL Along Sloped Side Surface of Semiconductor Die for Z-Direction Interconnect
US8796137B2 (en) * 2010-06-24 2014-08-05 Stats Chippac, Ltd. Semiconductor device and method of forming RDL along sloped side surface of semiconductor die for z-direction interconnect
US9437538B2 (en) 2010-06-24 2016-09-06 STATS ChipPAC Pte. Ltd. Semiconductor device including RDL along sloped side surface of semiconductor die for Z-direction interconnect

Also Published As

Publication number Publication date
WO2000014681A3 (fr) 2000-06-02
WO2000014681A2 (fr) 2000-03-16

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Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
8130 Withdrawal